Weak erase of a dummy memory cell to counteract inadvertent programming
A NAND string includes dummy memory cells between data memory cells and source-side and drain-side select gates. A gradual increase in threshold voltage (Vth) for the dummy memory cells which occurs due to program-erase cycles is periodically detected by a read operation at an upper checkpoint voltage. If the Vth has increased beyond the checkpoint, the control gate voltage of the dummy memory cells is decreased during subsequent erase operations of program-erase cycles, causing a gradual weak erase. A decrease in the Vth is later detected by a read operation at a lower checkpoint voltage. If the Vth has decreased too much, the control gate voltage is raised during subsequent erase operations, causing a gradual weak programming. The process can be repeated to keep the Vth within a desired range and avoid disturbs due to an increase in a channel voltage gradient which would otherwise occur.
1. A method for operating a memory device, comprising:
performing a first plurality of program-erase cycles involving a set of data memory cells, the set of data memory cells is eligible to store data, the set of data memory cells is in a plurality of NAND strings, each NAND string of the plurality of NAND string comprising a first dummy memory cell which is a non-data-storing memory cell and is provided between memory cells of the set which are in the NAND string and a select gate transistor of the NAND string, wherein each program-erase cycle of the first plurality of program-erase cycles comprises a program operation and an erase operation;
setting a first control gate voltage for the first dummy memory cells during erase operations of the first plurality of program-erase cycles;
after the first plurality of program-erase cycles, performing a first evaluation of threshold voltages of the first dummy memory cells, the performing the first evaluation comprises determining a first count of the first dummy memory cells which have a threshold voltage above an upper checkpoint voltage and determining whether or not the first count exceeds a threshold; and
if the first count exceeds the threshold, setting a second control gate voltage, lower than the first control gate voltage, for the first dummy memory cells during erase operations of a second plurality of program-erase cycles which are after the first plurality of program-erase cycles.
2. The method of claim 1 , further comprising:
determining a next time for performing a second evaluation of the threshold voltages of the first dummy memory cell based on whether or not the first count exceeds the threshold, wherein the next time is relatively sooner when the first count exceeds the threshold than when the first count does not exceed the threshold.
3. The method of claim 2 , wherein:
the next time for performing the second evaluation is set based on the first count.
4. The method of claim 1 , wherein:
the first plurality of program-erase cycles cause a gradual programming of the first dummy memory cells; and
the second plurality of program-erase cycles cause a gradual erase of the first dummy memory cells.
5. The method of claim 1 , further comprising:
if the first count does not exceed the threshold, setting the first control gate voltage for the first dummy memory cells during the erase operations of the second plurality of program-erase cycles.
6. The method of claim 1 , wherein:
the second control gate voltage is inversely proportional to the first count.
7. The method of claim 1 , further comprising:
if the first count exceeds the threshold, setting a third control gate voltage, higher than the second control gate voltage and lower than the first control gate voltage, for the first dummy memory cells during erase operations of a third plurality of program-erase cycles which are after the second plurality of program-erase cycles.
8. The method of claim 1 , further comprising:
after the first plurality of program-erase cycles, determining a second count of the first dummy memory cells which have a threshold voltage above the upper checkpoint voltage; and
setting a third control gate voltage for the first dummy memory cells during erase operations of a third plurality of program-erase cycles which are after the second plurality of program-erase cycles, wherein the third control gate voltage is inversely proportional to the second count.
9. The method of claim 1 , further comprising:
tracking a number of read operations experienced by the set of data memory cells, wherein the first evaluation is triggered based on the number of read operations.
10. The method of claim 1 , wherein:
tracking a number of program-erase cycles experienced by the set of data memory cells, wherein the first evaluation is triggered based on the number of program-erase cycles.
11. The method of claim 1 , further comprising:
after the second plurality of program-erase cycles, determining a second count of the first dummy memory cells which have a threshold voltage below a lower checkpoint voltage; and
if the second count exceeds a threshold, setting a third control gate voltage, higher than the second control gate voltage, for the first dummy memory cells during erase operations of a third plurality of program-erase cycles, after the second plurality of program-erase cycles.
12. The method of claim 11 , wherein:
the third control gate voltage is inversely proportional to the first count.
13. The method of claim 11 , wherein:
the first plurality of program-erase cycles cause a gradual programming of the first dummy memory cells;
the second plurality of program-erase cycles cause a gradual erase of the first dummy memory cells; and
the third plurality of program-erase cycles cause a gradual programming of the first dummy memory cells.
14. The method of claim 1 , wherein:
during the erase operations of the first plurality of program-erase cycles, the first control gate voltage is set for the first dummy memory cells while an erase voltage is applied to an end of each NAND string to charge up a channel of each NAND string; and
during the erase operations of the second plurality of program-erase cycles, the second control gate voltage is set for the first dummy memory cells while an erase voltage is applied to the end of each NAND string to charge up the channel of each NAND string.
15. The method of claim 1 , wherein each NAND string of the plurality of NAND string comprises a second dummy memory cell which is a non-data-storing memory cell and is provided between the first dummy memory cells of the NAND string and the select gate transistor of the NAND string, the method further comprising:
setting a first control gate voltage for the second dummy memory cells during the erase operations of the first plurality of program-erase cycles;
after the first plurality of program-erase cycles, determining a count of the second dummy memory cells which have a threshold voltage above an upper checkpoint voltage; and
if the count of the second dummy memory cells exceeds a threshold, setting a second control gate voltage for the second dummy memory cells during the erase operations of the second plurality of program-erase cycles, wherein the second control gate voltage for the second dummy memory cells is lower than the first control gate for the second dummy memory cells.
16. The method of claim 15 , wherein:
the first control gate voltage for the second dummy memory cells is different than the first control gate voltage for the first dummy memory cells;
the second control gate voltage for the first dummy memory cells is different than the second control gate voltage for the second dummy memory cells; and
the upper checkpoint voltage for the second dummy memory cells is different than the upper checkpoint voltage for the first dummy memory cells.
17. A 3D stacked non-volatile-memory device, comprising:
a control gate layer connected to first dummy memory cells which are non-data-storing memory cells;
a control gate layer connected to select gate transistors;
control gate layers connected to data memory cells, wherein the data memory cells are eligible to store data and the dummy memory cells are between the select gate transistors and the data memory cells, in a plurality of NAND strings; and
a control circuit, the control circuit is configured to:
perform at least one initial program-erase cycle for the data memory cells, wherein each program-erase cycle of the at least one first program-erase cycle comprises a program operation and an erase operation;
set a first control gate voltage for the first dummy memory cells during the erase operation of each program-erase cycle of the at least one initial program-erase cycle;
after the at least one initial program-erase cycle, determine a first count of the first dummy memory cells which have a threshold voltage above an upper checkpoint voltage; and
if the first count exceeds a threshold, set a second control gate voltage, lower than the first control gate voltage, for the first dummy memory cells during an erase operation of at least one additional program-erase cycle which is after the at least one initial program-erase cycle.
18. The 3D stacked non-volatile-memory device of claim 17 , wherein:
the second control gate voltage is inversely proportional to the first count.
19. The 3D stacked non-volatile-memory device of claim 17 , wherein:
if the first count exceeds the threshold, the control circuit is configured to set a third control gate voltage, higher than the second control gate voltage and lower than the first control gate voltage, for the first dummy memory cells during an erase operation of at least one further program-erase cycle which is after the at least one additional program-erase cycle.
20. The 3D stacked non-volatile-memory device of claim 17 , wherein:
after the at least one additional program-erase cycle, the control circuit is configured to determine a count of the first dummy memory cells which have a threshold voltage below a lower checkpoint voltage; and
if the count of the first dummy memory cells which have the threshold voltage below the lower checkpoint voltage exceeds a threshold, set a third control gate voltage, higher than the second control gate voltage, for the first dummy memory cells during an erase operation of at least one further program-erase cycle which is after the at least one additional program-erase cycle.
21. A memory controller, comprising:
a storage device comprising a set of instructions, the set of instructions comprising:
instructions for erasing one or more memory cells in a set of data memory cells, the set of data memory cells is eligible to store data and is in a plurality of NAND strings, each NAND string of the plurality of NAND string comprising a first dummy memory cell which is a non-data-storing memory cell and is provided between memory cells of the set which are in the NAND string and a select gate transistor of the NAND string;
instructions for setting a first control gate voltage for the first dummy memory cells during the erasing of the one or more memory cells in the set of data memory cells;
instructions for performing read operations involving the set of data memory cells, including applying at least one demarcation voltage to selected memory cells in the set while applying a pass voltage to unselected memory cells in the set;
instructions for determining a first count of the first dummy memory cells which have a threshold voltage above an upper checkpoint voltage, after the erasing of the one or more memory cells in the set of data memory cells and the read operations; and
instructions for setting a second control gate voltage, lower than the first control gate voltage, for the first dummy memory cells during a subsequent erase operation involving one or more memory cells in the set of data memory cells, if the first count exceeds a threshold; and
a processor operable to execute the set of instructions.
22. The memory controller of claim 21 , wherein the set of instructions further comprises:
instructions for tracking a number of the read operations and triggering the instructions for determining the first count based on the number of the read operations.
23. The memory controller of claim 21 , wherein the set of instructions further comprises:
instructions for tracking a number of program-erase cycles experienced by the set of data memory cells and triggering the instructions for determining the first count based on the number of program-erase cycles.