Fast programming memory device
In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.
1. A memory device comprising:
a data node;
a reference node;
word lines;
a group of non-volatile memory cells serially coupled between the data node and the reference node, the group of non-volatile memory cells coupled to the word lines such that each non-volatile memory cell of the group of non-volatile memory cells is coupled to one of the word lines; and
a control circuit operable to apply a same voltage to the word lines during retrieving of data from a selected non-volatile memory cell of the group of non-volatile memory.
2. The memory device of claim 1 , wherein the voltage comprises a reference voltage.
3. The memory device of claim 1 , wherein a value of the voltage is zero.
4. The memory device of claim 1 , wherein the data node comprises a bit line.
5. The memory device of claim 1 , wherein the reference node comprises a source line.
6. A memory device comprising:
a data node;
a source node;
a group of non-volatile memory cells serially coupled between the data node and the reference node, the group of non-volatile memory cells coupled to word lines such that each non-volatile memory cell of the group of non-volatile memory cells is coupled to one of the word lines; and
a control circuit operable to store data in a selected non-volatile memory cell of the group of non-volatile memory cells, to perform no verification of a state of the selected non-volatile memory cell after the data is stored in the selected non-volatile memory cell, and to apply a same voltage to the word lines during retrieving of the data from a selected non-volatile memory cell.
7. The memory device of claim 6 , wherein the control circuit is operable to store the data in the selected non-volatile memory cell such that after the data is stored in the selected non-volatile memory cell, the selected non-volatile memory cell has a state different from a state of other non-volatile memory cells in the group of non-volatile memory cells.
8. The memory device of claim 7 , wherein the state of the other non-volatile memory cells in the group of non-volatile memory cells comprises an erase state.
9. The memory device of claim 6 , wherein the control circuit is operable to store the data in the selected non-volatile memory cell in anticipation of the memory device transitioning from a first operating mode to a second operating mode.
10. The memory device of claim 9 , wherein the first operating mode comprises a full-power mode and the second operating mode comprises a less than full-power mode.
11. The memory device of claim 6 , wherein the control circuit is operable to use a single programming pulse to store the data in the selected non-volatile memory cell.
12. A method comprising:
storing data in a selected non-volatile memory cell of a group of non-volatile memory cells serially coupled between a data node and a source node, each non-volatile memory cell of the group of non-volatile memory cells coupled to a word line among word lines coupled to the group of non-volatile memory cells; and
applying a same voltage to the word lines coupled to the group of non-volatile memory cells during retrieving of the data from the selected non-volatile memory cell.
13. The method of claim 12 , wherein storing data in the selected non-volatile memory cell is performed such that the selected non-volatile memory cell has a state different from a state of other non-volatile memory cells in the group of non-volatile memory cells.
14. The method of claim 13 , wherein the state of the other non-volatile memory cells in the group of non-volatile memory cells comprises an erase state.
15. The method of claim 12 , wherein storing data in the selected non-volatile memory cell is performed using a single programming pulse.
16. The method of claim 12 , wherein storing data in the selected non-volatile memory cell is performed in anticipation of a memory device transitioning from a first operating mode to a second operating mode, the memory device comprising the group of non-volatile memory cells.
17. The method of claim 16 , wherein the first operating mode comprises a full-power mode and the second operating mode comprises a less than full-power mode.
18. The method of claim 12 , wherein the voltage comprises a reference voltage.
19. The method of claim 12 , wherein a value of the voltage is zero.
20. The method of claim 12 , wherein the data node comprises a bit line.