Granted Patent B2

US 9,317,462 · App. 14/659,074 · Granted Apr 19, 2016

Inventors: Guillaume Pean (Aix-en-Provence, FR); Franck Lunadier (Trets, FR); Alain Vergnes (Trets, FR)

Assignee: Atmel Corporation

G06F13/364G06F13/00G06F13/28G06F13/4022H04L9/0631

Abstract

Claims (80)

1. A device comprising:

a master module;

a peripheral module;

a data processing module; and

a system bus coupled to the master module, the peripheral module and the data processing module, the system bus configured to perform operations comprising:

receiving an instruction from the master module for a transfer of data associated with the peripheral module;

determining that the data to be transferred is to be processed by the data processing module before being received at its destination; and

based on a determination that the data is to be processed by the data processing module, redirecting the transfer to the data processing module.

2. The device of claim 1 , further comprising additional master modules and additional peripheral modules, wherein the determination that the data is to be processed by the data processing module comprises at least one of:

determining which master module initiated the transfer,

determining which peripheral module is associated with the transfer, or

determining a range of memory addresses corresponding to the data to be transferred.

3. The device of claim 1 , wherein redirecting the transfer to the data processing module comprises:

based on the determination that the data is to be processed by the data processing module, setting an extended address field in the system bus.

4. The device of claim 1 , wherein redirecting the transfer to the data processing module comprises:

determining whether an extended address field associated with the system bus is set by the master module; and

based on a determination that the extended address field associated with the system bus is set by the master module, redirecting the transfer to the data processing module.

5. The device of claim 1 , wherein the master module includes one of a microprocessor core, a direct memory access (DMA) controller, or a liquid crystal display (LCD) controller.

6. The device of claim 1 , wherein the peripheral module includes one of a memory controller, device memory, or an interrupt controller.

7. The device of claim 1 , wherein the data processing module includes a master interface and a slave interface, and wherein the data processing module is configured to perform operations comprising:

detecting, on the system bus, an indication that the data to be transferred is to be processed by the data processing module;

based on the detection, performing the transfer of the data to the data processing module;

processing the data; and

placing the processed data on the system bus.

8. The device of claim 7 , wherein detecting the indication comprises detecting that an extended address field is set in the system bus.

9. The device claim 8 , wherein the transfer is a read transfer, and wherein the data processing module is configured to perform operations comprising:

detecting the indication that the data to be transferred is to be processed by the data processing module using the slave interface;

based on the detection, performing the transfer of the data to the data processing module using the master interface, wherein performing the transfer of the data includes clearing the extended address field in the system bus; and

placing the processed data on the system bus using the slave interface.

10. The device of claim 8 , wherein the transfer is a write transfer, and wherein the data processing module is configured to perform operations comprising:

detecting the indication that the data to be transferred is to be processed by the data processing module using the slave interface;

based on the detection, performing the transfer of the data to the data processing module using the slave interface; and

writing the processed data to the peripheral module using the master interface, wherein writing the processed data to the peripheral module comprises clearing the extended address field in the system bus.

11. A device comprising:

a master module;

a peripheral module;

a system bus that is configured to process an instruction from the master module for transfer of data associated with the peripheral module; and

a data processing module that is coupled to the system bus, the data processing module configured to perform operations comprising:

detecting, on the system bus, an indication that the data to be transferred is to be processed by the data processing module before being received at its destination;

based on the detection, performing the transfer of the data to the data processing module;

processing the data; and

placing the processed data on the system bus.

12. The device of claim 11 , wherein data processing module includes a master interface and a slave interface, and wherein detecting the indication comprises detecting that an extended address field is set in the system bus.

13. The device of claim 11 , wherein the master module includes at least one of a microprocessor core, a direct memory access (DMA) controller, or a liquid crystal display (LCD) controller.

14. The device of claim 11 , wherein the peripheral module includes at least one of a memory controller, device memory, or an interrupt controller.

15. The device of claim 12 , wherein the transfer is a read transfer, and wherein the data processing module is configured to perform operations comprising:

detecting, using the slave interface, the indication that the data to be transferred is to be processed by the data processing module;

performing the transfer of the data to the data processing module using the master interface, wherein performing the transfer of the data includes clearing the extended address field in the system bus; and

placing the processed data on the system bus using the slave interface.

16. The device of claim 12 , wherein the transfer is a write transfer, and wherein the data processing module is configured to perform operations comprising:

detecting, using the slave interface, the indication that the data to be transferred is to be processed by the data processing module;

performing the transfer of the data to the data processing module using the slave interface; and

writing the processed data to a peripheral module using the master interface, wherein writing the processed data to the peripheral module comprises clearing the extended address field in the system bus.

17. The device of claim 12 , wherein the data processing module comprises a direct memory access (DMA) module included in the master interface, the DMA module configured to perform operations comprising:

performing the transfer of the data from a memory module to the data processing module for a read transfer; and

writing the processed data from the data processing module to a memory module for a write transfer.

18. The device of claim 12 , wherein the system bus is configured to set the extended address field based on a determination that the data to be transferred is to be processed by the data processing module before being received at its destination.

19. The device of claim 18 , wherein the device includes additional master modules and additional peripheral modules, and wherein the determination that the data to be transferred is to be processed by the data processing module comprises at least one of:

determining which master module initiated the transfer,

determining which peripheral module is associated with the transfer, or

determining a range of memory addresses corresponding to the data to be transferred.

20. A method comprising:

receiving, at a system bus, an instruction from a master module for a transfer of data associated with a peripheral module;

determining, by the system bus, that the data to be transferred is to be processed by the data processing module before being received at its destination; and

based on the determination that the data is to be processed by the data processing module, redirecting the transfer to the data processing module.

21. The method of claim 20 , wherein determining that the data is to be processed by the data processing module comprises at least one of:

determining which master module initiated the transfer,

determining which peripheral module is associated with the transfer, or

determining a range of memory addresses corresponding to the data to be transferred.

22. The method of claim 20 , wherein redirecting the transfer to the data processing module comprises:

based on the determination that the data is to be processed by the data processing module, setting, by the system bus, an extended address field in the system bus.

23. The method of claim 20 , wherein redirecting the transfer to the data processing module comprises:

determining whether an extended address field associated with the system bus is set by the master module; and

based on a determination that the extended address field associated with the system bus is set by the master module, redirecting the transfer to the data processing module.

24. The method of claim 20 , further comprising:

detecting, by the data processing module, an indication associated with the system bus that the data to be transferred is to be processed by the data processing module;

based on the detection, transferring, by the data processing module, the data to the data processing module;

processing, by the data processing module, the data; and

placing, by the data processing module, the processed data on the system bus.

25. The method of claim 24 , wherein detecting the indication comprises detecting that an extended address field is set in the system bus.

Assignments (10)

Continuity (2)