Integrated circuit packaging system with surface treatment and method of manufacture thereof
View Patent ↗An integrated circuit packaging system, and a method of manufacture thereof, includes: an embedded trace substrate having bonding sites and traces embedded in a base material, an insulation layer on the traces, the insulation layer having a top surface coplanar with the top surface of the base material; and an integrated circuit die connected to the bonding sites.
1. A method of manufacture of an integrated circuit packaging system comprising:
providing a base embedded trace substrate having traces and bonding sites embedded in a base material, the bonding sites lower than a top surface of the base material;
forming a mask over the bonding sites;
forming an insulation layer on the traces, the insulation layer having a top surface coplanar with a top surface of the base material;
removing the mask; and
connecting an integrated circuit die to the bonding sites; and
wherein:
forming the insulation layer includes forming the insulation layer on the bonding sites.
2. The method as claimed in claim 1 further comprising forming a protective layer on the bonding sites, the protective layer having a top surface higher than the top surface of the base material.
3. The method as claimed in claim 1 wherein providing the base embedded trace substrate includes providing the base embedded trace substrate having two traces between each of the bonding sites.
4. The method as claimed in claim 1 wherein providing the base embedded trace substrate includes providing the base embedded trace substrate having one of the traces between each of the bonding sites.
5. The method as claimed in claim 1 wherein forming the insulation layer includes forming a copper black or brown oxide.
6. A method of manufacture of an integrated circuit packaging system comprising:
providing a base embedded trace substrate having traces and bonding sites embedded in a base material, the bonding sites lower than a top surface of the base material;
forming a mask over the traces;
forming an insulation layer on the traces, the insulation layer having a top surface coplanar with a top surface of the base material; and
connecting an integrated circuit die to the bonding sites; and
wherein:
forming the insulation layer includes forming the insulation layer on the bonding sites.
7. The method as claimed in claim 6 further comprising forming a protective layer on the bonding sites, the protective layer having a top surface higher than the top surface of the base material.
8. The method as claimed in claim 6 further comprising forming an overhang portion of some of the bonding sites in direct contact with the top surface of the base material.
9. The method as claimed in claim 6 further comprising extending the bonding sites above the top surface of the base material.
10. The method as claimed in claim 6 wherein forming the mask includes forming the mask over the traces and on the insulation layer.
11. The method as claimed in claim 6 wherein:
forming the insulation layer on the traces includes forming the insulation layer on the bonding sites; and
removing the insulation layer on the bonding sites after forming the mask over the traces.
12. The method as claimed in claim 6 further comprising plating additional conductive material on the bonding sites for extending the bonding sites above the top surface of the base material.
13. The method as claimed in claim 6 further comprising depositing an underfill between the integrated circuit die and the insulation layer.
14. The method as claimed in claim 6 wherein forming the insulation layer includes forming a copper black or brown oxide.