IP Library › Granted Patent US 9,854,190
Granted Patent B2
US 9,854,190 · App. 14/667,436 · Granted Dec 26, 2017

Imaging systems and methods for transient signal integrity verification

Inventors: Frank James Demonte (Corvallis, OR); Cornelis Daniel Hoekstra (Corvallis, OR); Raymond Allen Davis (Salem, OR); Ray Alan Mentzer (Corvallis, OR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N5/3698H04N5/378H04N5/37455
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Quick Facts
Patent No.
US 9,854,190
App. No.
14/667,436
Granted
Dec 26, 2017
Kind
B2
Abstract

An image sensor with an array of pixels is provided. In order to determine failure of transient signal generation circuitry within the image sensor, monitoring circuitry may be used to capture and adjust transient signals as the signals are being transmitted. The transient signals may be voltage booster signals that are generated by booster circuitry to adjust row control signal levels to be below the ground reference voltage or above the supply reference voltage before providing them to the array of image sensor pixels. The captured and adjusted transient signals may be multiplexed and transmitted through a common buffer circuit. The method of shifting/adjusting the captured voltages may also apply to static signals. The multiplexed adjusted signals may be converted from digital signals to analog signals with digital-to-analog conversion circuitry. The digitized signals may be transmitted to host circuitry for processing which may include pass/fail testing.

Claims (48)

1. An imaging system, comprising:

an array of image sensor pixels;

row control circuitry comprising:

booster circuitry configured to generate transient voltage signals by adjusting voltage levels of row control signals for controlling individual rows of pixels in the array of image sensor pixels;

column control and readout circuitry;

transient signal monitoring circuitry that is configured to capture, store, and perform level adjustment operations on the transient voltage signals to generate level adjusted transient voltage signals; and

converting circuitry that performs analog-to-digital conversion on the level adjusted transient voltage signals.

2. The imaging system defined in claim 1 , wherein the converting circuitry comprises a column analog-to-digital converter circuit that is interposed on a column readout line coupled to the image pixel array.

3. The imaging system defined in claim 2 , wherein an output of the transient signal monitoring circuitry is coupled to the converting circuitry.

4. The imaging system defined in claim 1 , wherein the transient signal monitoring circuitry further comprises:

signal capturing circuitry that is configured to receive and store at least one of the generated transient voltage signals; and

level shifting and compressing circuitry that is configured to perform at least one of level shifting and compression operations on the stored at least one transient voltage signal to generate the level adjusted transient voltage signals.

5. The imaging system defined in claim 4 , wherein the generated transient voltage signals comprise a plurality of different transient voltage signals, wherein the signal capturing circuitry is further configured to receive and store each of the plurality of different transient voltage signals, and wherein the level shifting and compressing circuitry comprises a corresponding level shifting and compressing circuit that is configured to perform at least one of the level shifting and compression operations on each respective transient voltage signal of the stored plurality of different transient voltage signals.

6. The imaging system defined in claim 5 , wherein the level shifting and compressing circuitry further comprises:

multiplexing circuitry that routes each of the plurality of different transient voltage signals through a common buffer circuit interposed between the level shifting and compressing circuitry and the converting circuitry.

7. The imaging system defined in claim 5 , wherein the level shifting and compressing circuit further comprises:

first and second capacitors; and

a reference voltage signal input.

8. The imaging system defined in claim 7 , wherein the level shifting and compressing circuit is further configured to perform at least one of the level shifting and compression operations based on a magnitude of the reference voltage signal input and a capacitance ratio of the first and second capacitors.

9. A system, comprising:

a central processing unit;

memory;

a lens;

input-output circuitry; and

an imaging device, wherein the imaging device comprises:

an image pixel array arranged in rows and columns;

row control circuitry;

column control and readout circuitry;

booster circuitry that is configured to adjust row control signal voltage levels for the rows of the image pixel array to generate booster signals;

transient signal monitoring circuitry that is configured to capture, store, and perform level adjustment operations on the booster signals to generate level adjusted booster signals; and

converting circuitry that performs analog-to-conversion on the level adjusted booster signals.

10. The system defined in claim 9 , wherein the transient signal monitoring circuitry further comprises:

signal capturing circuitry that is configure to receive and store the generated booster signals; and

level shifting and compressing circuitry that is configured to perform at least one of level shifting and compression operations on the stored booster signals to generate the level adjusted booster signals.

11. The system defined in claim 10 , wherein the generated booster signals comprises a plurality of different booster signals, wherein the signal capturing circuitry is further configured to receive and store each of the plurality of different booster signals, and wherein the level shifting and compressing circuitry comprises a corresponding level shifting and compressing circuit that is configured to perform at least one of the level shifting and compression operations on each respective booster signal of the stored plurality of different transient voltage signals.

12. The system defined in claim 11 , wherein the level shifting and compressing circuit further comprises:

first and second capacitors; and

a reference voltage signal input.

13. The system defined in claim 12 , wherein the level shifting and compressing circuit is further configured to perform at least one of the level shifting and compression operations based on the magnitude of the reference voltage signal input and a capacitance ratio of the first and second capacitors.

14. An imaging system comprising:

booster circuitry that generates a boosted row control signal for controlling a row of image sensor pixels;

signal capturing circuitry that captures and stores the boosted row control signal;

level shifting and compressing circuitry that performs at least one of compression and level shifting operations on the captured and stored boosted row control signal; and

converting circuitry that converts the boosted row control signal from an analog signal to a digital signal.

15. The imaging system defined in claim 14 , wherein the signal capturing circuitry captures and stores the boosted row control signal in response to receiving a booster sample enable signal at the signal capturing circuitry.

16. The imaging system defined in claim 14 , wherein the level shifting and compressing circuitry comprises first and second capacitors, and wherein the level shifting and compressing circuitry compresses the boosted row control signal by a capacitance ratio of the first and second capacitors.

17. The imaging system defined in claim 16 , wherein the level shifting and compressing circuitry level shifts the boosted row control signal to a predetermined offset magnitude based on a reference voltage signal.

18. The imaging system defined in claim 14 , wherein the converting circuitry transmits the converted boosted row control signal to host circuitry for processing.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2015
From: DEMONTE, FRANK JAMES; HOEKSTRA, CORNELIS DANIEL; DAVIS, RAYMOND ALLEN; MENTZER, RAY ALAN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 035245/0681 →
Continuity (1)
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