Memory cells with read access schemes
View Patent ↗Memory cells with read assist schemes and methods of use are provided. The memory includes a plurality of rows and columns, each of which include a memory cell having a pull-down device. The memory further includes at least one boost circuit connected to each of the memory cells and which provides a negative boost signal to the pull-down devices during read access.
1. A memory comprising:
a plurality of rows and columns, each of which include a memory cell having a pull-down device; and
at least one boost circuit connected to each of the memory cells and which provides a negative boost signal to the pull-down devices during read access.
2. The memory of claim 1 , wherein the at least one boost circuit is a charge pump.
3. The memory of claim 1 , wherein the at least one boost circuit is commonly connected to each of the memory cells.
4. The memory of claim 1 , wherein the at least one boost circuit is two or more boost circuits.
5. The memory of claim 4 , wherein each of the memory cells in each column is commonly connected to a single boost circuit.
6. The memory of claim 1 , wherein the at least one boost circuit strengthens the pull-down device of each memory cell during the read access.
7. The memory of claim 6 , wherein the at least one boost circuit brings the pull-down device to a higher Vgs during the read access thereby boosting a bitcell low voltage reference (VBOOST 1 ) during the read access.
8. The memory of claim 7 , wherein the at least one boost circuit increases a pull-down on the bitcell low voltage reference, BTL 0 .
9. The memory of claim 7 , wherein a circuit switches on and off boost capacitance of the boost circuit during the read access and write operations, respectively.
10. The memory of claim 9 , wherein the at least one boost circuit includes a negatively charged capacitor and a transistor which turns off during the read access such that the pull-down device of the memory cell is provided with a negative charge of the negatively charged capacitor.
11. The memory of claim 10 , wherein the transistor is turned on during write operations, connecting the pull-down device is connected to GND.
12. A memory, comprising:
a memory cell comprising a crossover inverter comprising a pull-up device and a pull-down device connected to bitlines through access transistors; and
a boost circuit connected to the pull-down devices and providing a negative boost signal to the pull-down device during read access.
13. The memory of claim 12 , wherein the boost circuit is a charge pump.
14. The memory of claim 13 , wherein the charge pump comprises a negatively charged capacitor and a transistor connecting to ground and the pull-down device.
15. The memory of claim 14 , wherein when the transistor is on it connects the pull-down device to ground during write operations.
16. The memory of claim 15 , wherein when the transistor is off it connects the pull-down device to a negative charge during the read access.
17. The memory of claim 12 , wherein the boost circuit strengthens the pull-down device by increasing Vgs during the read access and boosting a bitcell low voltage reference (BTL 0 ).
18. The memory of claim 12 , wherein the boost circuit switches on and off boost capacitance during the read access and write operations, respectively.
19. The memory of claim 12 , wherein the pull-down devices are a pair of NFETs, and the boost control is connected to the source of the NFETs.
20. A method comprising boosting negatively a bitcell of a memory device during a read access.