FinFET structures having silicon germanium and silicon fins
A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region.
1. A method comprising:
depositing an epitaxial carbon doped silicon layer on an essentially undoped silicon substrate;
depositing an epitaxial silicon germanium layer on the carbon doped silicon layer;
depositing an essentially undoped epitaxial silicon layer on the silicon germanium layer, thereby forming a first structure comprising the silicon substrate, the carbon doped silicon layer, the silicon germanium layer and the epitaxial silicon layer;
forming a shallow trench isolation region within the first structure;
removing the silicon germanium layer on a first side of the shallow trench isolation region, thereby forming a space within the first structure beneath the epitaxial silicon layer;
filling the space with an electrically insulating material;
thermally mixing the silicon germanium layer and the epitaxial silicon layer on a second side of the shallow trench isolation region, thereby forming a silicon germanium surface layer;
forming a first set of parallel fins from the epitaxial silicon layer on the first side of the shallow trench isolation region, and
forming a second set of parallel fins from the silicon germanium surface layer on the second side of the shallow trench isolation region.
2. The method of claim 1 , wherein the electrically insulating material comprises an oxide.
3. The method of claim 1 , further including the step of forming one or more p-type FinFET devices using the second set of parallel fins.
4. The method of claim 1 , wherein the step of forming the space within the first structure beneath the epitaxial silicon layer includes forming a trench through the epitaxial silicon layer and etching the silicon germanium layer.