Memory system and method for reducing read disturb errors

1. A memory system comprising:

a memory comprising a plurality of blocks; and

a controller in communication with the memory, wherein the controller is configured to:

determine that there is a read disturb error in a block;

identify which data in the block caused the read disturb error to occur in other data in the block; and

relocate the data that caused the read disturb error to another block with a higher read endurance than the block currently storing the data, wherein the another block with the higher read endurance is less susceptible to read disturb errors than the block currently storing the data.

2. The memory system of claim 1 , wherein the controller is further configured to relocate the data to a block with a lower read endurance after the data is determined to be less likely to cause a read disturb error when read.

3. The memory system of claim 1 , wherein the read disturb error is determined using a read counter.

4. The memory system of claim 1 , wherein the read disturb error is determined using a read-patrol technique.

5. The memory system of claim 1 , wherein the read disturb error is determined by reading neighboring word lines when reading a word line.

6. The memory system of claim 1 , wherein the controller is configured to identify data in the block that is causing the read disturb error using read counters.

7. The memory system of claim 1 , wherein the block with the higher read endurance comprises SLC memory cells, and wherein the block in which the read disturb error was determined comprises MLC memory cells.

8. The memory system of claim 1 , wherein the block with the higher read endurance comprises volatile memory, and wherein the block in which the read disturb error was determined comprises non-volatile memory.

9. The memory system of claim 1 , wherein the block with the higher read endurance stores dummy data in word lines surrounding the word lines that store the data.

10. The memory system of claim 1 , wherein the memory is a three-dimensional memory.

11. The memory system of claim 1 , wherein the memory system is embedded in a host.

12. The memory system of claim 1 , wherein the memory system is removably connected to a host.

13. A memory system comprising:

a memory comprising a plurality of blocks;

a plurality of read counters; and

a read disturb module in communication with the memory and the plurality of read counters, wherein the read disturb module is configured to:

sense a read disturb error in a first block;

copy data from the first block to a second block;

assign read counters to the second block to identify hot read data;

copy the hot read data from the second block to a third block, wherein the third block is less susceptible to read disturb errors than the first block;

assign read counters to the third block to determine when the hot read data becomes cold read data; and

copy the cold read data from the third block to another block.

14. The memory system of claim 13 , wherein the read disturb module is configured to sense read disturb errors using a read counter.

15. The memory system of claim 13 , wherein the read disturb module is configured to sense read disturb errors using a read-patrol technique.

16. The memory system of claim 13 , wherein the read disturb module is configured to sense read disturb errors by reading neighboring word lines when reading a word line.

17. The memory system of claim 13 , wherein the third block has a higher read endurance than the first block.

18. The memory system of claim 13 , wherein the first block comprises MLC memory cells, and wherein the third block comprises SLC memory cells.

19. The memory system of claim 13 , wherein the first block comprises non-volatile memory, and wherein the third block comprises volatile memory.

20. The memory system of claim 13 , wherein the third block stores dummy data in word lines surrounding the word lines that store the data.

21. The memory system of claim 13 , wherein the memory is a three-dimensional memory.

22. The memory system of claim 13 , wherein the memory system is embedded in a host.

23. The memory system of claim 13 , wherein the memory system is removably connected to a host.

24. The memory system of claim 13 , wherein hot read data becomes cold read data when reading the hot read data will no longer result in a read disturb error.

25. The memory system of claim 13 , wherein hot read data becomes cold read data when read activity of the hot read data is below a threshold.

26. The memory system of claim 1 , wherein less than all of the data in the block is relocated to the block with the higher read endurance.

27. The memory system of claim 26 , wherein only the data that caused the read disturb error is relocated to the block with the higher read endurance.

28. A memory system comprising:

a memory comprising a plurality of blocks; and

means for determining that there is a read disturb error in a block;

means for identifying which data in the block caused the read disturb error to occur in other data in the block; and

means for relocating the data that caused the read disturb error to another block with a higher read endurance than the block currently storing the data, wherein the another block with the higher read endurance is less susceptible to read disturb errors than the block currently storing the data.

29. The memory system of claim 28 further comprising means for relocating the data to a block with a lower read endurance after the data is determined to be less likely to cause a read disturb error when read.

30. The memory system of claim 28 , wherein the block with the higher read endurance comprises SLC memory cells, and wherein the block in which the read disturb error was determined comprises MLC memory cells.