Method of manufacturing a FinFET device using a sacrificial epitaxy region for improved fin merge and FinFET device formed by same
A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors.
1. A fin field-effect transistor (FinFET) device, comprising:
a substrate;
a first plurality of fins on the substrate corresponding to a first transistor;
a second plurality of fins on the substrate corresponding to a second transistor;
a first epitaxy region extending between the first plurality of fins;
a second epitaxy region extending between the second plurality of fins; and
a dielectric layer on the substrate, wherein a portion of the dielectric layer is positioned between the first epitaxy region and the second epitaxy region preventing contact between the first epitaxy region and the second epitaxy region;
wherein the first epitaxy region extends over an entirety of the first plurality of fins and the second epitaxy region extends over an entirety of the second plurality of fins;
wherein a height of the first epitaxy region is greater than a height of the first plurality of fins and a height of the second epitaxy region is greater than a height of the second plurality of fins; and
wherein the height of the second epitaxy region over a first fin of the second plurality fins is different from the height of the second epitaxy region over a second fin of the second plurality fins.
2. The FinFET device according to claim 1 , wherein the first and second plurality of fins are formed on a buried oxide layer.
3. The FinFET device according to claim 1 , wherein the height of the first epitaxy region is in the range of 10 nm to 20 nm greater than the height of the first plurality of fins and the height of the second epitaxy region over a portion of the second plurality of fins is in the range of 10 nm to 20 nm greater than the height of the second plurality of fins.
4. The FinFET device according to claim 1 , wherein the first transistor has a first doping.
5. The FinFET device according to claim 4 , wherein the first epitaxy region comprises phosphorous doped silicon.
6. The FinFET device according to claim 5 , wherein the second transistor has a second doping.
7. The FinFET device according to claim 6 , wherein the second epitaxy region comprises boron doped silicon.
8. The FinFET device according to claim 1 , wherein the first and second epitaxy regions are doped differently.
9. An electronic device, comprising:
a semiconductor device, the semiconductor device comprising:
a substrate;
a first plurality of fins on the substrate corresponding to a first transistor;
a second plurality of fins on the substrate corresponding to a second transistor;
a first epitaxy region extending between the first plurality of fins;
a second epitaxy region extending between the second plurality of fins; and
a dielectric layer on the substrate, wherein a portion of the dielectric layer is positioned between the first epitaxy region and the second epitaxy region preventing contact between the first epitaxy region and the second epitaxy region;
wherein the first epitaxy region extends over an entirety of the first plurality of fins and the second epitaxy region extends over an entirety of the second plurality of fins;
wherein a height of the first epitaxy region is greater than a height of the first plurality of fins and a height of the second epitaxy region is greater than a height of the second plurality of fins; and
wherein the height of the second epitaxy region over a first fin of the second plurality fins is different from the height of the second epitaxy region over a second fin of the second plurality fins.
10. The electronic device according to claim 9 , wherein the first and second plurality of fins are formed on a buried oxide layer.
11. The electronic device according to claim 9 , wherein the height of the first epitaxy region is in the range of 10 nm to 20 nm greater than the height of the first plurality of fins and the height of the second epitaxy region over a portion of the second plurality of fins is in the range of 10 nm to 20 nm greater than the height of the second plurality of fins.
12. The electronic device according to claim 9 , wherein the first transistor has a first doping.
13. The electronic device according to claim 12 , wherein the first epitaxy region comprises phosphorous doped silicon.
14. The electronic device according to claim 13 , wherein the second transistor has a second doping.
15. The electronic device according to claim 14 , wherein the second epitaxy region comprises boron doped silicon.
16. The electronic device according to claim 9 , wherein the first and second epitaxy regions are doped differently.