IP Library Granted Patent US 9,417,798
Granted Patent B2
US 9,417,798 · App. 14/700,411 · Granted Aug 16, 2016

Card and host device

Inventor: Akihisa Fujimoto (Fussa, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
G06F3/061G06F3/0659G06F3/0679G06F2206/1014
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Quick Facts
Patent No.
US 9,417,798
App. No.
14/700,411
Granted
Aug 16, 2016
Kind
B2
Abstract

A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

Claims (23)

1. A memory card comprising:

a memory; and

a controller which

controls the memory,

receives from a host device a first command which includes a voltage identification section which has a bit pattern selected from two bit patterns, the bit pattern indicating voltages which the host device supports,

determines whether the memory card supports the voltages indicated by the bit pattern in the voltage identification section of the first command, and

issues a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command when the memory card determines that the memory card supports the voltages indicated by the bit pattern in the voltage identification section of the first command.

2. The card of claim 1 , wherein

the memory card does not issue a response when the memory card determines that the memory card does not support the voltages indicated by the bit pattern in the voltage identification section of the first command.

3. The card of claim 1 , wherein:

the first command further includes an error detection code section which has an error detection code and a check pattern section which has a bit pattern, and

the memory card issues the response which further includes an error detection section which has an error detection code and a check pattern section which has the same bit pattern as the bit pattern in the check pattern section of the first command.

4. A host device which:

reads and writes data from and into a memory card,

issues a first command which includes a voltage identification section which has a bit pattern selected from two bit patterns, the bit pattern indicating voltages which the host device supports,

performs initialization of the memory card when the host device receives a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command, and

terminates initialization of the memory card when the host device does not receive a response to the first command.

5. The device of claim 4 , wherein:

the first command further includes an error detection code section which has an error detection code and a check pattern section which has a bit pattern, and

the host device performs initialization of the memory card when the host device receives the response which further includes an error detection section which has an error detection code which indicates no error and a check pattern section which has the same bit pattern as the bit pattern in the check pattern section of the first command.

6. The device of claim 4 , wherein:

the host device issues an initialization command which instructs the memory card to perform initialization when the host device receives a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command, and

the host device does not issue an initialization command which instructs the memory card to perform initialization when the host device does not receive a response which includes a voltage identification section which has the same bit pattern as the bit pattern in the voltage identification section of the first command.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043328/0388 →
Priority Claims (1)
JP PCT/JP04/17627 · Nov 26, 2004 · national
Continuity (12)
Continuation 14457720 · Aug 12, 2014
Continuation 14079130 · Nov 13, 2013
Continuation 13772016 · Feb 20, 2013
Continuation 13614749 · Sep 13, 2012
Continuation 13422916 · Mar 16, 2012
Continuation 13010346 · Jan 20, 2011
Continuation 12861114 · Aug 23, 2010
Continuation 12468886 · May 20, 2009
Continuation 12043005 · Mar 5, 2008
Continuation 11553002 · Oct 26, 2006
Continuation PCTJP2005021689 · Nov 25, 2005
Related Publication 20150234596A1 · Aug 20, 2015