Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays
Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
1. A split-gate non-volatile memory (NVM) cell array, comprising:
select gate structures for a plurality of split-gate NVM cells within the split-gate NVM cell array formed using a first material layer;
dummy select gate structures also formed using the first material layer;
control gate structures for the plurality of split-gate NVM cells formed using a second material layer and a non-patterned spacer etch;
charge storage layers for the plurality of split-gate NVM cells associated with the select gate structures and the control gate structures;
contact landing regions between the dummy select gate structures and the select gate structures, the contact landing regions being formed using the second material layer and the non-patterned spacer gate etch used to form the control gate structures; and
electrical contacts coupled to the contact landing regions;
wherein each of the plurality of split-gate NVM cells comprises one of the charge storage layers formed between one of the select gate structures and one of the control gate structures.
2. The split-gate NVM cell array of claim 1 , wherein the first material layer and the second material layer comprises doped polysilicon.
3. The split-gate NVM cell array of claim 1 , wherein at least one dummy select gate structure is located between two select gate lines for the split-gate NVM cell array.
4. The split-gate NVM cell array of claim 1 , wherein at least one dummy select gate structure is located at longitudinal ends of two select gate lines within the split-gate NVM cell array.
5. The split-gate NVM cell array of claim 4 , further comprising at least one additional dummy select gate structure located between the two select gate lines.
6. The split-gate NVM cell array of claim 5 , wherein at least one contact landing region is associated with the additional dummy select gate structure.
7. A split-gate non-volatile memory (NVM) cell array, comprising:
select gate structures formed using a first material layer;
dummy select gate structures also formed using the first material layer;
control gate structures formed using a second material layer and a non-patterned spacer etch;
charge storage layers associated with the select gate structures and the control gate structures;
contact landing regions between the dummy select gate structures and the select gate structures, the contact landing regions being formed using the second material layer and the non-patterned spacer gate etch used to form the control gate structures; and
electrical contacts coupled to the contact landing regions;
wherein at least one dummy select gate structure is located between two select gate lines for the split-gate NVM cell array; and
wherein at least one contact landing region is associated with a control-gate strap between the two select gate lines, the control-gate strap including the at least one dummy select gate structure.
8. A split-gate non-volatile memory (NVM) cell array, comprising:
select gate structures formed using a first material layer;
dummy select gate structures also formed using the first material layer;
control gate structures formed using a second material layer and a non-patterned spacer etch;
charge storage layers associated with the select gate structures and the control gate structures;
contact landing regions between the dummy select gate structures and the select gate structures, the contact landing regions being formed using the second material layer and the non-patterned spacer gate etch used to form the control gate structures; and
electrical contacts coupled to the contact landing regions;
wherein at least one dummy select gate structure is located between two select gate lines for the split-gate NVM cell array; and
further comprising at least one select gate tab associated with the dummy select gate structure, the select-gat tab extending from the at least one select gate structure towards a dummy select gate structure and comprising the first material.
9. A split-gate non-volatile memory (NVM) cell array, comprising:
select gate structures formed using a first material layer;
dummy select gate structures also formed using the first material layer;
control gate structures formed using a second material layer and a non-patterned spacer etch;
charge storage layers associated with the select gate structures and the control gate structures;
contact landing regions between the dummy select gate structures and the select gate structures, the contact landing regions being formed using the second material layer and the non-patterned spacer gate etch used to form the control gate structures; and
electrical contacts coupled to the contact landing regions;
wherein at least one dummy select gate structure is located at longitudinal ends of two select gate lines within the split-gate NVM cell array; and
wherein at least one contact landing region is associated with a control-gate wrap connection adjacent the two select gate lines, the wrap connection including the at least one dummy select gate structure.
10. A split-gate non-volatile memory (NVM) cell array, comprising:
select gate structures formed using a first material layer;
dummy select gate structures also formed using the first material layer;
control gate structures formed using a second material layer and a non-patterned spacer etch;
charge storage layers associated with the select gate structures and the control gate structures;
contact landing regions between the dummy select gate structures and the select gate structures, the contact landing regions being formed using the second material layer and the non-patterned spacer gate etch used to form the control gate structures; and
electrical contacts coupled to the contact landing regions;
wherein the contact landing regions comprise sloped edges extending from select gate structures and sloped edges extending from dummy select gate structures.
11. A split-gate non-volatile memory (NVM) cell array, comprising:
select gate structures formed using a first material layer;
dummy select gate structures also formed using the first material layer;
control gate structures formed using a second material layer and a non-patterned spacer etch;
charge storage layers associated with the select gate structures and the control gate structures;
contact landing regions between the dummy select gate structures and the select gate structures, the contact landing regions being formed using the second material layer and the non-patterned spacer gate etch used to form the control gate structures; and
electrical contacts coupled to the contact landing regions;
wherein for each dummy select gate structure, a distance from an edge for the dummy select gate structure to an edge for a select gate structure is equal to or less than about 1.5 to 2.0 times the thickness of the control gate layer.