Method and structure for determining thermal cycle reliability
View Patent ↗A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.
1. A test structure used to determine reliability performance, comprising:
a patterned metallization structure having a plurality of interfaces, which form stress risers, the metallization structure including at least one of:
a via chain formed through layers of patterned metallization in the semiconductor structure such that a plurality of widths of vias are used to adjust strain in different layers; and
a dummy structure formed to provide a via density in an area of the semiconductor structure to adjust strain in adjacent structures of the test structure; and
a dielectric material surrounding the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exists such that failures occur under given stress conditions to provide a yield indicative of reliability for a manufacturing design.
2. The structure as recited in claim 1 , further comprising:
dummy structures not electrically connected to the metallization structure and placed near ends of the test structure to reduce the variation in thermal strain at corner or end vias.
3. The structure as recited in claim 1 , wherein the metallization structure is separated from metal pads to reduce thermal expansion effects caused by the metal pads.
4. The structure as recited in claim 3 , wherein the distance between the metallization structure and the bond pads is such that a reduction in thermal strain of any via is within 5% of a maximum value of thermal strain that exists between the metallization structure and the dielectric material for a completely isolated via.
5. The structure as recited in claim 1 , wherein the metallization structure further comprises multiple sections electrically connected and separated by a distance to reduce thermal expansion effects caused by adjacent vias.
6. The structure as recited in claim 5 , wherein the distance between the sections is such that a reduction in thermal strain of any section is within 5% of a maximum value of thermal strain that exists between the metallization structure and the dielectric material for a completely isolated section of vias.
7. The structure as recited in claim 1 , wherein the same strain value is employed across all of the vias in the test structure.
8. The structure as recited in claim 1 , wherein the mismatch in CTE between the metallization structure and the dielectric material is greater than about 20 ppm/° C.
9. The structure as recited in claim 1 , wherein the dummy structures are not electrically connected to the metallization structure and are placed near ends of the test structure to reduce the variation in thermal strain at corner or end vias.
10. The structure as recited in claim 1 , wherein the metallization structure further comprises multiple sections electrically connected and separated by a distance to reduce thermal expansion effects caused by adjacent vias.