Forming resistive random access memories together with fuse arrays
A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
1. A method comprising:
forming a chalcogenide memory array including forming select devices by forming two sets of orthogonal trenches, wherein said forming a chalcogenide memory array includes performing a process flow; and
forming a fuse array on a same substrate as the chalcogenide memory array, wherein said forming the fuse array includes performing the process flow.
2. The method of claim 1 , wherein the two sets of orthogonal trenches extend into the fuse array.
3. The method of claim 1 , wherein the two sets of orthogonal trenches includes a first set of parallel trenches and a second set of parallel trenches perpendicular to said first set of parallel trenches; and
wherein said forming a fuse array includes forming a third set of parallel trenches.
4. The method of claim 3 wherein the third set of parallel trenches is oriented in the same direction as the first set of parallel trenches.
5. The method of claim 3 wherein said forming the fuse array further includes forming a fourth set of parallel trenches, the fourth set of parallel trenches being perpendicular to the third set of parallel trenches.
6. The method of claim 5 wherein the fourth set of parallel trenches is oriented in the same direction as the second set of parallel trenches.
7. The method of claim 1 , wherein said select devices are transistors.
8. The method of claim 7 , wherein the transistors are bipolar junction transistors.
9. The method of claim 7 , wherein the transistors are NMOS transistors.
10. The method of claim 1 , wherein the fuse cell array further comprises a select transistor for each fuse cell.
11. A method comprising:
forming two sets of orthogonal trenches for select devices of a chalcogenide memory array that is formed on a substrate; and
forming a fuse array on the substrate, wherein the two sets of orthogonal trenches extend into the fuse array.
12. The method of claim 11 , further comprising forming a conductive line in at least one trench of at least one set of the two sets of orthogonal trenches in the fuse array.
13. The method of claim 12 , further comprising forming an address line transverse to the conductive line.
14. The method of claim 13 , wherein the address line includes a fuse.
15. The method of claim 13 , wherein the address line includes a first portion and a second portion separated by a gap.
16. The method of claim 15 , further comprising forming a fuse on the first portion or the second portion of the address line.
17. The method of claim 13 , further comprising forming fuses at an intersection of the address line and the conductive line.
18. The method of claim 13 , further comprising forming a second address line transverse to the conductive line, wherein the second address line does not overlap the conductive line.
19. The method of claim 11 , further comprising:
forming conductive lines in at least one of the two sets of orthogonal trenches in the fuse array; and
forming address lines transverse to the conductive lines, wherein the address lines comprise first and second portions separated by gaps.
20. The method of claim 19 , further comprising:
forming fuses at intersections of the address lines and the conductive lines, wherein at least some of the first or second portions of the address lines are shorter than other first or second portions so that at least some of the first and second portions of the address lines do not overlap the conductive lines.