Integrated micro-peltier cooling components in silicon-on-insulator (SOI) layers

1. A method of forming an integrated circuit (IC) device, the method comprising:

forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device;

forming a first oxide layer over the handle wafer covering the thermoelectric cooling device;

forming a second oxide layer over a donor silicon wafer to form a donor wafer;

bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and

forming at least one semiconductor device over a side of the donor wafer opposite the second oxide layer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.

2. The method of claim 1 , further comprising: analyzing a data file representing the IC device during operation to determine the location of the elevated temperature region, using a computing device including a processor.

3. The method of claim 2 , wherein the location of the elevated temperature region is determined by comparing a temperature of a plurality of regions in the IC with temperature design conditions for each of the plurality of regions to determine whether at least one of the plurality of regions exceeds a corresponding temperature design condition.

4. The method of claim 1 , wherein the at least one thermoelectric cooling device is formed to contact the upper surface of the handle wafer during the forming.

5. The method of claim 1 , further comprising cleaving the donor wafer through the donor silicon wafer to form a silicon-on-insulator substrate prior to the forming of the at least one semiconductor device.

6. The method of claim 5 , further comprising forming a through-silicon-via (TSV) proximate the at least one semiconductor device and extending through the donor wafer to contact the thermoelectric cooling device.

7. The method of claim 6 , wherein the forming of the TSV include forming the TSV to further extend through the handle waver to contact a lower surface of the handle wafer.

8. The method of claim 7 , wherein the TSV contacts the thermoelectric cooling device on a side of the thermoelectric cooling device.

9. A method of forming an integrated circuit (IC) device, the method comprising: forming at least one semiconductor device over a silicon-on-insulator (SOI) substrate, the SOI substrate having: a first silicon layer; at least one thermoelectric cooling device over an upper surface of the first silicon layer; an oxide layer over the first silicon layer and the at least one thermoelectric cooling device; and a second silicon layer over the oxide layer wherein the at least one semiconductor device is formed over the second silicon layer; and forming at least one through silicon via (TSV) from a region proximate the at least one semiconductor device in the second silicon layer, through the oxide layer, to contact the at least one thermoelectric cooling device, wherein the at least one semiconductor device is located in an elevated temperature region of the IC device, and wherein a location of the at least one thermoelectric cooling device is determined to vertically correspond with the elevated temperature region.

10. The method of claim 9 , further comprising: analyzing a data file representing the IC device during operation to determine the location of the elevated temperature region, using a computing device including a processor.

11. The method of claim 10 , wherein the location of the elevated temperature region is determined by comparing a temperature of a plurality of regions in the IC with temperature design conditions for each of the plurality of regions to determine whether at least one of the plurality of regions exceeds a corresponding temperature design condition.

12. The method of claim 9 , wherein the at least one thermoelectric cooling device contacts the upper surface of the handle wafer.

13. The method of claim 9 , wherein the forming of the at least one TSV includes forming a plurality of TSVs from regions proximate the at least one semiconductor device in the second silicon layer, through the oxide layer, to contact the at least one thermoelectric cooling device.

14. The method of claim 9 , further comprising forming at least one additional TSV from an underside of the first silicon layer, through the first silicon layer, to contact the at least one thermoelectric cooling device.

15. The method of claim 9 , wherein the forming of the at least one TSV includes forming the at least one TSV to extend alongside the at least one thermoelectric cooling device and through the first silicon layer to contact an underside of the first silicon layer.

16. A method of forming an integrated circuit (IC) device, the method comprising: running a functional simulation on a data file used to form the IC device, the functional simulation indicating a temperature of each of a plurality of regions in the IC device; identifying at least one elevated temperature region in the plurality of regions as having a simulated temperature greater than a temperature design condition; forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon the location of the elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide on the handle wafer; and forming at least one semiconductor device over a side of the donor wafer opposite the second oxide layer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.

17. The method of claim 16 , wherein the at least one thermoelectric cooling device is formed to contact the upper surface of the handle wafer during the forming.

18. The method of claim 16 , further comprising cleaving the donor wafer through the donor silicon wafer to form a silicon-on-insulator substrate prior to the forming of the at least one semiconductor device.

19. The method of claim 18 , further comprising forming a through-silicon-via (TSV) proximate the at least one semiconductor device and extending through the donor wafer to contact the thermoelectric cooling device.

20. The method of claim 19 , wherein the forming of the TSV include forming the TSV to further extend through the handle waver to contact a lower surface of the handle wafer, wherein the TSV contacts the thermoelectric cooling device on a side of the thermoelectric cooling device.