IP Library Granted Patent US 9,519,747
Granted Patent B1
US 9,519,747 · App. 14/751,222 · Granted Dec 13, 2016

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table

Inventors: Nathan Buck (Underhill, VT); Brian M. Dreibelbis (Underhill, VT); John P. Dubuque (Jericho, VT); Eric A. Foreman (Fairfax, VT); David J. Hathaway (Underhill, VT); Jeffrey G. Hemmett (St. George, VT); Kerim Kalafala (Rhinebeck, VT); Gregory M. Schaeffer (Poughkeepsie, NY); Stephen G. Shuma (Underhill, VT); Natesan Venkateswaran (Hopewell Junction, NY); Chandramouli Visweswariah (Croton-on-Hudson, NY); Vladimir Zolotov (Putnam Valley, NY)
Assignee: GLOBALFOUNDRIES INC.
G06F17/5081G06F17/5022G06F17/5031G06F2217/84
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Quick Facts
Patent No.
US 9,519,747
App. No.
14/751,222
Granted
Dec 13, 2016
Kind
B1
Abstract

Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Claims (61)

1. A method for performing a static timing analysis used in integrated circuit chip design, said method comprising:

receiving an integrated circuit design into a computerized device;

performing an analysis of said integrated circuit design to identify characteristics of physical features of portions of said integrated circuit design, using said computerized device; and

determining sensitivities of timing values of different portions, respectively, of said integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables), using said computerized device, wherein, for each portion of said integrated circuit design, a sensitivity of a timing value is determined by:

evaluating, by said computerized device, relationships between said characteristics of physical features of said portion of said integrated circuit design to generate an indicator value;

determining whether said indicator value is outside or within a table usage filter value range;

when said indicator value is outside said table usage filter value range, calculating, by said computerized device, a calculated sensitivity value for said sensitivity of said timing value to said PVT variables; and

when said indicator value is within said table usage filter range, looking up, by said computerized device, a previously determined sensitivity value for said sensitivity of said timing value to said PVT variables from a look-up table, wherein said look-up table is stored in a memory that is accessible by said computerized device and wherein using said look-up table reduces a runtime and memory requirements for said static timing analysis while maintaining accuracy.

2. The method according to claim 1 , said determining of said sensitivities comprising: using previously established sensitivity importance criteria to use different table usage filter value ranges for different portions of said integrated circuit design.

3. The method according to claim 2 , said previously established sensitivity importance criteria being different for at least one of:

different physical layers of said integrated circuit design;

different physical locations of said integrated circuit design;

different materials within said integrated circuit design; and

different parameters of said PVT variables.

4. The method according to claim 1 , said evaluating of said relationships between said characteristics of physical features of said portion of said integrated circuit design comprising calculating ratios of physical sizes, electrical values, and timing values of said physical features.

5. The method according to claim 1 , further comprising updating said look-up table during determining of said sensitivity of said timing value to said PVT variables.

6. The method according to claim 5 , said updating using results from said calculating of said calculated sensitivity value for said sensitivity of said timing value to said PVT variables to update said look-up table.

7. The method according to claim 1 , said calculating of said calculated sensitivity value for said sensitivity of said timing value to said PVT variables comprising one of:

finite differences modeling;

current source modeling; and

non-linear delay modeling.

8. A method for performing a static timing analysis used in integrated circuit chip design, said method comprising:

creating a look-up table of previously determined timing value sensitivity with respect to characteristics of physical features of portions of integrated circuit designs and storing said look-up table in a memory accessible by a computerized device;

receiving an integrated circuit design into said computerized device;

performing an analysis of said integrated circuit design to identify characteristics of physical features of portions of said integrated circuit design, using said computerized device; and

determining sensitivities of timing values of different portions, respectively, of said integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables), using said computerized device, wherein, for each portion of said integrated circuit design, a sensitivity of a timing value is determined by:

evaluating, by said computerized device, relationships between said characteristics of physical features of said portion of said integrated circuit design to generate an indicator value;

determining whether said indicator value is outside or within a table usage filter value range;

when said indicator value is within said table usage filter value range, calculating, by said computerized device, a calculated sensitivity value for said sensitivity of said timing value to said PVT variables; and

when said indicator value is within said table usage filter range, looking up a previously determined sensitivity value for said sensitivity of said timing value to said PVT variables from said look-up table, wherein using said look-up table reduces a runtime and memory requirements for said static timing analysis while maintaining accuracy.

9. The method according to claim 8 , said determining of said sensitivities comprising: using previously established sensitivity importance criteria to use different table usage filter value ranges for different portions of said integrated circuit design.

10. The method according to claim 9 , said previously established sensitivity importance criteria being different for at least one of:

different physical layers of said integrated circuit design;

different physical locations of said integrated circuit design;

different materials within said integrated circuit design; and

different parameters of said PVT variables.

11. The method according to claim 8 , said evaluating of said relationships between said characteristics of physical features of said portion of said integrated circuit design comprising calculating ratios of physical sizes, electrical values, and timing values of said physical features.

12. The method according to claim 8 , further comprising updating said look-up table during determining of said sensitivity of said timing value to said PVT variables.

13. The method according to claim 12 , said updating using results from said calculating of said calculated sensitivity value for said sensitivity of said timing value to said PVT variables to update said look-up table.

14. The method according to claim 8 , said calculating of said calculated sensitivity value for said sensitivity of said timing value to said PVT variables comprising one of:

finite differences modeling;

current source modeling; and

non-linear delay modeling.

15. A computer program product for performing an analysis, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions being executable by a computerized device to cause the computerized device to perform a method for performing a static timing analysis used in integrated circuit chip design, the method comprising:

creating a look-up table of previously determined timing value sensitivity with respect to characteristics of physical features of portions of integrated circuit designs and storing said look-up table in a memory accessible by said computerized device;

receiving an integrated circuit design into said computerized device;

performing an analysis of said integrated circuit design to identify characteristics of physical features of portions of said integrated circuit design, using said computerized device; and

determining sensitivities of timing values of different portions, respectively, of said integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables), using said computerized device, wherein, for each of portion of said integrated circuit design, a sensitivity of a timing value is determined by:

evaluating relationships between said characteristics of physical features of said portion of said integrated circuit design to generate an indicator value;

determining whether said indicator value is outside or within a table usage filter value range;

when said indicator value is outside said table usage filter value range, calculating a calculated sensitivity value for said sensitivity of said timing value to said PVT variables; and

when said indicator value is within said table usage filter range, looking up a previously determined sensitivity value for said sensitivity of said timing value to said PVT variables from said look-up table, wherein using said look-up table reduces a runtime and memory requirements for said static timing analysis while maintaining accuracy.

16. The computer program product according to claim 15 , said determining of said sensitivities comprising: using previously established sensitivity importance criteria to use different table usage filter value ranges for different portions of said integrated circuit design.

17. The computer program product according to claim 16 , said previously established sensitivity importance criteria being different for at least one of:

different physical layers of said integrated circuit design;

different physical locations of said integrated circuit design;

different materials within said integrated circuit design; and

different parameters of said PVT variables.

18. The computer program product according to claim 15 , said evaluating of said relationships between said characteristics of physical features of said portion of said integrated circuit design comprising calculating ratios of physical sizes, electrical values, and timing values of said physical features.

19. The computer program product according to claim 15 , further comprising updating said look-up table during determining of said sensitivity of said timing value to said PVT variables.

20. The computer program product according to claim 19 , said updating using results from said calculating of said calculated sensitivity value for said sensitivity of said timing value to said PVT variables to update said look-up table.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2019
From: GLOBALFOUNDRIES U.S. INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051070/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2019
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 050122/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2016
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 037542/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2016
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 037409/0869 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2015
From: BUCK, NATHAN; DREIBELBIS, BRIAN M.; DUBUQUE, JOHN P.; FOREMAN, ERIC A.; HATHAWAY, DAVID J.; HEMMETT, JEFFREY G.; KALAFALA, KERIM; SCHAEFFER, GREGORY M.; SHUMA, STEPHEN G.; VENKATESWARAN, NATESAN; VISWESWARIAH, CHANDRAMOULI; ZOLOTOV, VLADIMIR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 036021/0001 →