IP Library Granted Patent US 9,520,174
Granted Patent B2
US 9,520,174 · App. 14/754,635 · Granted Dec 13, 2016

Method and apparatus for writing to a magnetic tunnel junction (MTJ) by applying incrementally increasing voltage level

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Quick Facts
Patent No.
US 9,520,174
App. No.
14/754,635
Granted
Dec 13, 2016
Kind
B2
Abstract

A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.

Claims (9)

1. A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array comprising:

a. selecting a word line that is coupled to an MTJ to be written;

b. applying a voltage pulse with a voltage level of V x to a source line coupled to the MTJ;

c. reading a state of the MTJ after applying the voltage pulse;

d. comparing the state of the read MTJ to a value in a write latch;

e. determining if a desired state is written to the read MTJ; and

f. if the MTJ is determined not to be written to the desired state, increasing the voltage level and re-applying the voltage pulse with the increased voltage level and repeating steps c. through f. until the MTJ is written to the desired state.

2. The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 1 , wherein the desired state is same as an in-coming data.

3. The method of writing to a magnetic tunnel junction (MTJ), as recited in claim 1 , wherein an access transistor is coupled to the MTJ and the word line is coupled to the access transistor and wherein upon writing the desired state into the MTJ, de-selecting the word line.

Assignments (6)
SECURITY INTEREST Recorded Mar 18, 2022
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 059436/0203 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057213/0050 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057217/0674 →
SECURITY INTEREST Recorded Jul 8, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: SILICON VALLEY BANK
Reel/Frame 053156/0223 →
SECURITY INTEREST Recorded Feb 13, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 051930/0396 →
SECURITY INTEREST Recorded Apr 18, 2017
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 042273/0813 →