Semiconductor device and manufacturing method thereof
A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.
1. A semiconductor device comprising:
an integrated circuit;
at least one outer seal ring surrounding the integrated circuit, wherein the at least one outer seal ring comprises a plurality of metal layers in a stacked configuration, and the plurality of the metal layers are closed loops;
a dielectric layer having first and second portions; and
at least one inner seal ring disposed between the at least one outer seal ring and the integrated circuit and separated from the at least one outer seal ring, wherein the at least one inner seal ring comprises a plurality of metal layers in a stacked configuration along a first direction and has first and second seal portions separated from each other by the first portion of the dielectric layer along a second direction transverse to the first direction and third and fourth seal portions spaced apart from the first and second seal portions, separated from each other by the second portion of the dielectric layer, and in the same layer as the first and second seal portions.
2. The semiconductor device of claim 1 , wherein a number of the at least one outer seal ring is at least two, and the at least one outer seal rings are separated from each other.
3. The semiconductor device of claim 1 , wherein the integrated circuit comprises at least one analog circuit and at least one digital circuit.
4. The semiconductor device of claim 1 , wherein the first, second, third, and fourth seal portions are arranged along a first side of the integrated circuit.
5. The semiconductor device of claim 4 , further comprising a plurality of seal portions arranged along a second side of the integrated circuit opposite the first side of the integrated circuit.
6. The semiconductor device of claim 4 , further comprising a plurality of seal portions arranged along a second side of the integrated circuit adjacent the first side of the integrated circuit.
7. The semiconductor device of claim 6 , further comprising a plurality of seal portions arranged along a third side of the integrated circuit adjacent the second side of the integrated circuit.
8. The semiconductor device of claim 1 , further comprising:
a second dielectric layer having a dielectric portion aligned with the first portion of the dielectric layer along the first direction, wherein the at least one inner seal ring further comprises fifth and sixth seal portions in a different layer than the first and second seal portions and separated from each other by the dielectric portion of the second dielectric layer along the second direction.
9. The semiconductor device of claim 1 , further comprising an isolation in a substrate, wherein the first portion of the dielectric layer is aligned with the isolation along the first direction.
10. A semiconductor device comprising:
an integrated circuit;
at least one outer seal ring disposed around the integrated circuit, wherein the at least one outer seal ring comprises a plurality of metal layers in a stacked configuration along a first direction, and the plurality of the metal layers surround the integrated circuit continuously;
a dielectric layer having first and second portions; and
at least one inner seal ring disposed between the at least one outer seal ring and the integrated circuit and separated from the at least one outer seal ring, wherein the at least one inner seal ring comprises first and second seal portions separated from each other by the first portion of the dielectric layer and third and fourth seal portions spaced apart from the first and second seal portions, separated from each other by the second portion of the dielectric layer, and in the same layer as the first and second seal portions and the first, second, third, and fourth seal portions are aligned with each other along a second direction transverse to the first direction.
11. The semiconductor device of claim 10 , wherein the at least one outer seal ring further comprises a plurality of contacts respectively disposed between two adjacent ones of the plurality of the metal layers.
12. The semiconductor device of claim 10 , further comprising:
a substrate disposed beneath the integrated circuit, the at least one outer seal ring, and the at least one inner seal ring.
13. The semiconductor device of claim 10 , wherein a number of the at least one outer seal ring is at least two, and the at least one outer seal rings are separated from each other.
14. The semiconductor device of claim 10 , wherein a number of the at least one inner seal ring is at least two, and the at least one inner seal rings are disposed between the at least one outer seal ring and the integrated circuit.
15. A semiconductor device comprising:
an integrated circuit;
a dielectric layer having first and second portions; and
a seal ring surrounding the integrated circuit, wherein the seal ring comprises a plurality of metal layers in a stacked configuration along a first direction and has a plurality of seal portions that surround first and second corners of the integrated circuit, first seal portions of the plurality of the seal portions are separated from each other by the first portion of the dielectric layer along a second direction transverse to the first direction, second seal portions of the plurality of the seal portions are separated from each other by the second portion of the dielectric layer along a third direction transverse to the first and second directions, and the first seal portions are in the same layer as the second seal portions.
16. The semiconductor device of claim 15 , wherein the first and second corners of the integrated circuit are adjacent corners.
17. The semiconductor device of claim 15 , further comprising a closed loop second seal ring surrounding the integrated circuit.
18. The semiconductor device of claim 17 , wherein the integrated circuit comprises analog and digital circuits respectively at the first and second corners of the integrated circuit.
19. The semiconductor device of claim 15 , wherein the plurality of the seal portions further surround a third corner of the integrated circuit.
20. The semiconductor device of claim 19 , wherein the plurality of the seal portions further surround a fourth corner of the integrated circuit.