Granted Patent B2

US 12,199,049 · App. 18/446,166 · Granted Jan 14, 2025

Inventor: Hsien-Wei Chen (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

H01L23/562H01L23/53209H01L23/585

Abstract

Claims (45)

1. A semiconductor structure, comprising:

a substrate having a seal ring region and a circuit region;

a dielectric layer over the substrate;

a connection structure disposed in the seal ring region, wherein the connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers;

a first metal plug disposed below the connection structure and disposed at least partially in the dielectric layer in the seal ring region;

a second metal plug disposed below the connection structure and coplanar with the first metal plug, wherein one of the first metal plug or the second metal plug has a surface below a top surface of the substrate; and

a dummy gate disposed in the dielectric layer and between the first metal plug and the second metal plug.

2. The semiconductor structure of claim 1 , further comprising:

wherein each of the first metal plug and the second metal plug has a surface below the top surface of the substrate.

3. The semiconductor structure of claim 1 , wherein the first metal plug and the second metal plug include cobalt.

4. The semiconductor structure of claim 3 , wherein the cobalt of the first metal plug has a first width at a first region and a second width at a second region above the first region, the first and second widths measured in a cross-sectional view.

5. The semiconductor structure of claim 1 , wherein each of the first metal plug and the second metal plug have multiple sections of different widths in a cross-sectional view.

6. The semiconductor structure of claim 1 , wherein the dummy gate is between the first metal plug and the second metal plug in a top view.

7. The semiconductor structure of claim 6 , wherein the first metal plug is a ring-like structure and the second metal plug is a ring-like structure in the top view.

8. The semiconductor structure of claim 6 , wherein at least one of the first metal plug and the second metal plug are segmented ring structures in the top view.

9. The semiconductor structure of claim 1 , further comprising:

a dielectric layer disposed on a sidewall of an upper portion of the first metal plug; and a silicide layer disposed on a sidewall of a lower portion of the first metal plug.

10. A semiconductor structure, comprising:

a substrate having a seal ring region surrounding a circuit region;

a dielectric layer disposed on the substrate;

a connection structure disposed in the dielectric layer in the seal ring region, wherein the connection structure includes metal layers in a stacking configuration;

a first metal plug disposed between the substrate and the connection structure in the seal ring region, wherein the first metal plug includes a cobalt layer and a conductive layer below the cobalt layer, wherein the cobalt layer has at least two steps in a cross-sectional view; and

a first metal via disposed on the first metal plug and connecting the first metal plug to the connection structure.

11. The semiconductor structure of claim 10 , wherein the first metal plug has a ring structure that surrounds the circuit region from a top view.

12. The semiconductor structure of claim 10 , further comprising a first gate structure between the substrate and the connection structure in the seal ring region.

13. The semiconductor structure of claim 12 , wherein the first gate structure and the first metal plug are coplanar.

14. The semiconductor structure of claim 12 , further comprising:

a second metal plug disposed between the seal ring region of the substrate and the connection structure in the seal ring region, wherein the second metal plug includes a cobalt layer and a conductive layer surrounding below the cobalt layer, wherein the cobalt layer has at least two steps in a cross-sectional view.

15. The semiconductor structure of claim 14 , wherein the first gate structure interposes the second metal plug and the first metal plug in a top view.

16. A method, comprising:

forming a dielectric layer over a substrate having a seal ring region and a circuit region;

forming a first trench into the dielectric layer and the substrate in the seal ring region;

increasing a width of the first trench in the dielectric layer thereby providing a second trench above and contiguous with the first trench;

filling the first trench and the second trench with conductive material to form a plug, respectively; and

forming a stack of metal layers and metal vias vertically connecting the stack of metal layers over the substrate, wherein at least one via of the metal vias is formed on the plug.

17. The method of claim 16 , further comprising:

forming another dielectric layer over the dielectric layer, wherein the second trench extends through the another dielectric layer; and

increasing a width of the second trench in the another dielectric layer thereby forming a third trench above and contiguous with the second trench and the first trench;

and wherein the filling the first trench and the second trench includes filling the third trench.

18. The method of claim 16 , further comprising:

forming a silicide layer on a portion of the substrate that is exposed by the first trench; and forming a conductive barrier layer.

19. The method of claim 16 , before filling the first trench and the second trench, forming a dielectric liner on sidewalls of the second trench.

20. The method of claim 19 , wherein the forming the dielectric liner includes:

depositing a dielectric liner material by an atomic layer deposition (ALD);

patterning the dielectric liner material to remove the deposited dielectric liner material from sidewalls of the first trench.

Assignments (1)

Continuity (5)

References Cited (28)