IP Library Granted Patent US 9,635,762
Granted Patent B2
US 9,635,762 · App. 14/803,889 · Granted Apr 25, 2017

Semiconductor package

Inventors: Shinji Watanabe (Kanagawa, JP); Sumikazu Hosoyamada (Kanagawa, JP); Shingo Nakamura (Kanagawa, JP); Hiroshi Demachi (Kanagawa, JP); Takeshi Miyakoshi (Kanagawa, JP); Tomoshige Chikai (Kanagawa, JP); Kiminori Ishido (Kanagawa, JP); Hiroaki Matsubara (Kanagawa, JP); Takashi Nakamura (Kanagawa, JP); Hirokazu Honda (Kanagawa, JP); Yoshikazu Kumagaya (Kanagawa, JP); Shotaro Sakumoto (Kanagawa, JP); Toshihiro Iwasaki (Kanagawa, JP); Michiaki Tamakawa (Kanagawa, JP)
Assignee: J-DEVICES CORPORATION
H05K1/181H01L23/36H01L23/3675H01L23/3677H01L23/3733H01L23/4334H01L25/105H05K1/0204H01L23/3128H01L23/49816H01L2224/16227H01L2224/32225H01L2224/45144H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73265H01L2225/1023H01L2225/1058H01L2225/1094H01L2924/15331H01L2924/1815H05K2201/0275H05K2201/066H05K2201/10515
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Quick Facts
Patent No.
US 9,635,762
App. No.
14/803,889
Granted
Apr 25, 2017
Kind
B2
Abstract

A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

Claims (23)

1. A stacked semiconductor package, comprising:

a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board;

a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and

a heat transfer layer provided over the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device,

wherein the first circuit board includes a thermal via extending through the first circuit board,

the heat transfer layer is in contact with the first semiconductor device and the first circuit board, and is connected to the thermal via,

the heat transfer layer includes a first heat transfer layer and a second heat transfer layer, and

the second heat transfer layer having a thermal conductivity lower than the thermal conductivity in the thickness direction of the first heat transfer layer and having a heat-insulating property.

2. The stacked semiconductor package according to claim 1 ,

wherein the first semiconductor package includes a plurality of joining electrode terminals joined with the second semiconductor package and provided around the first semiconductor device, and

the heat transfer layer is located inner to the plurality of joining electrode terminals.

3. The stacked semiconductor package according to claim 1 ,

wherein the first semiconductor package includes a plurality of joining electrode terminals joined with the second semiconductor package and provided around the first semiconductor device, and

the heat transfer layer is provided on substantially an entire surface of the first semiconductor package while enclosing the plurality of joining electrode terminals.

4. The stacked semiconductor package according to claim 1 , wherein the thermal via is in contact with a power supply plane or a ground plane included in the first circuit board.

5. The stacked semiconductor package according to claim 1 , wherein the heat transfer layer has a thermal conductivity in a planar direction higher than a thermal conductivity thereof in a thickness direction.

6. The stacked semiconductor package according to claim 1 , wherein the heat transfer layer is formed of any one of carbon fiber prepreg, carbon fiber sheet and carbon graphite sheet.

7. The stacked semiconductor package according to claim 1 ,

wherein the second heat transfer layer and the second circuit board are separated from each other.

8. The stacked semiconductor package according to claim 1 , further comprising a sealing resin provided on a top surface of the heat transfer layer.

9. The stacked semiconductor package according to claim 1 , wherein the heat transfer layer has a shape of a cross having a width smaller than a length of each of sides of the first semiconductor device.

10. The stacked semiconductor package according to claim 1 , wherein the heat transfer layer has a cutout as seen in a plan view.

11. The stacked semiconductor package according to claim 7 , wherein the first heat transfer layer is arranged on the side of the first circuit board with respect to the second heat transfer layer, and the second heat transfer layer is arranged on the side of the second circuit board with respect to the first heat transfer layer.

Assignments (2)
CHANGE OF NAME Recorded Jul 17, 2020
From: J-DEVICES CORPORATION
To: AMKOR TECHNOLOGY JAPAN, INC.
Reel/Frame 053242/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2015
From: WATANABE, SHINJI; HOSOYAMADA, SUMIKAZU; NAKAMURA, SHINGO; DEMACHI, HIROSHI; MIYAKOSHI, TAKESHI; CHIKAI, TOMOSHIGE; ISHIDO, KIMINORI; MATSUBARA, HIROAKI; NAKAMURA, TAKASHI; HONDA, HIROKAZU; KUMAGAYA, YOSHIKAZU; SAKUMOTO, SHOTARO; IWASAKI, TOSHIHIRO; TAMAKAWA, MICHIAKI
To: J-DEVICES CORPORATION
Reel/Frame 036137/0389 →
Priority Claims (1)
JP 2014-150374 · Jul 24, 2014 · national
Continuity (1)
Related Publication 20160027715A1 · Jan 28, 2016