IP Library Granted Patent US 9,466,644
Granted Patent B2
US 9,466,644 · App. 14/807,370 · Granted Oct 11, 2016

Resistance-switching memory cell with multiple raised structures in a bottom electrode

Inventors: George Matamis (San Jose, CA); James K Kai (Santa Clara, CA); Vinod R Purayath (Santa Clara, CA); Yuan Zhang (San Jose, CA); Henry Chien (San Jose, CA)
Assignee: SanDisk Technologies LLC
H01L27/2463H01L27/2481H01L45/04H01L45/06H01L45/1233H01L45/1253H01L45/1273H01L45/144H01L45/145H01L45/146H01L45/147H01L45/149H01L45/16H01L45/1675
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Quick Facts
Patent No.
US 9,466,644
App. No.
14/807,370
Granted
Oct 11, 2016
Kind
B2
Abstract

A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Claims (42)

1. A resistance-switching memory cell, comprising:

a substrate;

a bottom electrode layer above the substrate, the bottom electrode layer comprising a plurality of raised structures;

a resistance-switching material, a top of each raised structure of the plurality of raised structures is in contact with the resistance-switching material;

a top electrode above the resistance-switching material; and

an insulating material adjacent to and between the plurality of raised structures, wherein a top of the insulating material is below the top of each raised structure of the plurality of raised structures and the resistance-switching material extends above the plurality of raised structures and the insulating material.

2. The resistance-switching memory cell of claim 1 , wherein:

the top of the insulating material is above a bottom of each raised structure of the plurality of raised structures.

3. The resistance-switching memory cell of claim 1 , wherein:

less than one-third of a cross-sectional area of the resistance-switching memory cell is consumed by the plurality of raised structures.

4. The resistance-switching memory cell of claim 1 , wherein:

a top surface of the insulating material is adjacent to a bottom surface of the resistance-switching material.

5. The resistance-switching memory cell of claim 1 , wherein:

the plurality of raised structures are spaced apart from one another in a plurality of rows.

6. The resistance-switching memory cell of claim 1 , wherein:

the plurality of raised structures are spaced apart from one another in a first direction and in a second direction which is perpendicular to the first direction.

7. The resistance-switching memory cell of claim 1 , wherein:

the plurality of the raised structures are not joined to one another.

8. The resistance-switching memory cell of claim 1 , wherein:

the plurality of the raised structures are joined to one another at a bottom of the bottom electrode layer.

9. The resistance-switching memory cell of claim 1 , wherein:

the bottom electrode layer comprises doped polysilicon.

10. The resistance-switching memory cell of claim 1 , wherein:

the resistance-switching material comprises a phase change material.

11. The resistance-switching memory cell of claim 1 , wherein:

the resistance-switching material comprises a metal oxide.

12. A resistance-switching memory device, comprising:

a substrate;

a bottom wiring layer on the substrate comprising spaced apart wires; and

a plurality of resistance-switching memory cells formed on the substrate and aligned with the spaced apart wires of the bottom wiring layer, wherein each resistance-switching memory cell comprises:

a plurality of raised structures in a bottom electrode layer above the substrate, wherein each raised structure of the plurality of raised structures has a top, and the plurality of raised structures are spaced apart from one another in a first direction and in a second direction which is perpendicular to the first direction,

a resistance-switching material, wherein a top of each raised structure of the plurality of raised structures is in contact with the resistance-switching material;

a top electrode above the resistance-switching material; and

an insulating material between the plurality of raised structures, wherein a top of the insulating material is at a height which is below a height of the top of each raised structure of the plurality of raised structures, and the resistance-switching material extends above the plurality of raised structures and the insulating material.

13. The resistance-switching memory device of claim 12 , further comprising:

a top wiring layer comprising spaced apart wires aligned with, and in electrical contact with, rows of the top electrodes.

14. The resistance-switching memory device of claim 12 , further comprising:

a top wiring layer comprising spaced apart wires aligned with rows of the resistance-switching memory cells, the top electrodes are provided by portions of the spaced apart wires.

15. The resistance-switching memory device of claim 12 , wherein:

the resistance-switching material of each of the resistance-switching memory cells are separated from one another.

16. The resistance-switching memory device of claim 12 , wherein:

the resistance-switching memory cells as formed as pillars which are spaced apart from one another.

Assignments (4)
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038812/0954 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 25, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038520/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: SANDISK 3D LLC.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038300/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2015
From: MATAMIS, GEORGE; KAI, JAMES K; PURAYATH, VINOD R; ZHANG, YUAN; CHIEN, HENRY
To: SANDISK 3D LLC
Reel/Frame 036181/0912 →
Continuity (2)
Division 13767663 · Feb 14, 2013
Related Publication 20150333105A1 · Nov 19, 2015