IP Library Granted Patent US 9,123,890
Granted Patent B2
US 9,123,890 · App. 13/767,663 · Granted Sep 1, 2015

Resistance-switching memory cell with multiple raised structures in a bottom electrode

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Quick Facts
Patent No.
US 9,123,890
App. No.
13/767,663
Granted
Sep 1, 2015
Kind
B2
Abstract

A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Claims (51)

1. A resistance-switching memory cell, comprising:

a substrate;

a plurality of raised structures in a bottom electrode layer above the substrate, wherein the plurality of raised structures are spaced apart from one another in a plurality of rows;

a resistance-switching material, wherein a top of each raised structure of the plurality of raised structures is in contact with the resistance-switching material; and

a top electrode above the resistance-switching material.

2. The resistance-switching memory cell of claim 1 , wherein:

the plurality of the raised structures are raised structures in a layer of doped polysilicon; and

adjacent raised structures of the plurality of raised structures are not joined to one another by portions of the layer of doped polysilicon.

3. The resistance-switching memory cell of claim 1 , wherein:

the plurality of the raised structures are raised structures in a layer of doped polysilicon; and

portions of the layer of doped polysilicon join adjacent raised structures of the plurality of raised structures to one another at a bottom of the bottom electrode layer.

4. The resistance-switching memory cell of claim 1 , wherein:

the resistance-switching material extends laterally adjacent to the plurality of raised structures and above the plurality of raised structures.

5. The resistance-switching memory cell of claim 1 , wherein:

the bottom electrode layer comprises doped polysilicon having a doping concentration of 1×10^18/cm^3 or higher.

6. The resistance-switching memory cell of claim 1 , wherein:

the resistance-switching material comprises a phase change material.

7. The resistance-switching memory cell of claim 1 , wherein:

the resistance-switching material comprises a metal oxide.

8. The resistance-switching memory cell of claim 1 , wherein:

each raised structure has a width of no more than 2-9 nm.

9. The resistance-switching memory cell of claim 1 , wherein:

the plurality of raised structures are uniformly spaced apart from one another in a first direction and in a second direction which is perpendicular the first direction.

10. The resistance-switching memory cell of claim 1 , wherein:

each row of the plurality of rows comprises multiple raised structures of the plurality of raised structures.

11. A resistance-switching memory device, comprising:

a substrate;

a bottom wiring layer on the substrate comprising spaced apart wires; and

a plurality of resistance-switching memory cells formed on the substrate and aligned with the spaced apart wires of the bottom wiring layer, wherein each resistance-switching memory cell comprises:

a plurality of pillars in a bottom electrode layer above the substrate, wherein each pillar has a top, and the plurality of pillars are spaced apart from one another in a first direction and in a second direction which is perpendicular the first direction,

a resistance-switching material, wherein the tops of the pillars are is in contact with the resistance-switching material and spaced apart from one another, and

a top electrode above the resistance-switching material.

12. The resistance-switching memory device of claim 11 , further comprising:

a top wiring layer comprising spaced apart wires aligned with, and in electrical contact with, rows of the top electrodes.

13. The resistance-switching memory device of claim 11 , further comprising:

a top wiring layer comprising spaced apart wires aligned with rows of the resistance-switching memory cells, the top electrodes are provided by portions of the spaced apart wires.

14. The resistance-switching memory device of claim 11 , wherein:

the resistance-switching material of each of the resistance-switching memory cells is separated from one another.

15. The resistance-switching memory device of claim 11 , wherein:

each pillar has a circular cross-section.

16. The resistance-switching memory device of claim 11 , wherein for each resistance-switching memory cell:

the plurality of pillars are uniformly spaced apart from one another in the first direction and in the second direction.

17. The resistance-switching memory device of claim 11 , wherein for each resistance-switching memory cell:

the plurality of pillars are spaced apart from one another in a plurality of rows.

18. The resistance-switching memory device of claim 11 , wherein for each resistance-switching memory cell:

the plurality of pillars are dispersed in the bottom electrode layer.

19. The resistance-switching memory device of claim 11 , wherein:

each resistance-switching memory cell comprises a pillar; and

the bottom electrode layer and the resistance-switching material of each resistance-switching memory cell are provided in the pillar of the resistance-switching memory cell.

20. The resistance-switching memory device of claim 19 , wherein:

each pillar has a circular cross-section.

Assignments (7)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0898 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 25, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038520/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: SANDISK 3D LLC.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038300/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2013
From: MATAMIS, GEORGE; KAI, JAMES K; PURAYATH, VINOD R; ZHANG, YUAN; CHIEN, HENRY
To: SANDISK 3D LLC
Reel/Frame 029819/0854 →