Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof

1. A semiconductor wafer comprising:

a semiconductor substrate having a first substrate surface and a second substrate surface;

a plurality of build up layers on the first substrate surface, wherein the plurality of build up layers include conductive layers and conductive vias that are electrically coupled to device terminals that are located over the first substrate surface in a device area of the substrate;

a plurality of first through substrate vias extending between the first and second substrate surfaces, wherein the plurality of first through substrate vias includes a first subset of one or more trench vias each having a primary axis aligned in a first direction, and a second subset of one or more trench vias each having a primary axis aligned in a second direction that is different from the first direction, and the plurality of first through substrate vias form an alignment pattern in an alignment area of the substrate;

a second through substrate via extending between the first and second substrate surfaces in the device area of the substrate; and

a conductive layer directly connected to the second substrate surface and to first ends of the plurality of first through substrate vias, wherein the conductive layer is patterned so that a first portion of the conductive layer is directly coupled to the plurality of first through substrate vias, and a second portion of the conductive layer is directly coupled to the second through substrate via, and wherein a conductive material void is present, at the second substrate surface, in the conductive layer.

2. The semiconductor wafer of claim 1 , wherein the conductive layer comprises:

a seed metal layer directly coupled to the second substrate surface; and

a thick metal layer coupled to the seed layer.

3. The semiconductor wafer of claim 2 , wherein the thick metal layer has a thickness in a range of 10 microns to 50 microns.

4. The semiconductor wafer of claim 1 , further comprising:

a transistor formed at the first substrate surface, wherein the second through substrate via is electrically coupled to the transistor.

5. The semiconductor wafer of claim 1 , wherein the first ends of the plurality of first through substrate vias have relative positions with respect to the second substrate surface that are selected from a position that is slightly recessed from the second substrate surface, a position that is slightly above the second substrate surface, and a position that is substantially co-planar with the second substrate surface.

6. The semiconductor wafer of claim 1 , wherein the first direction is orthogonal to the second direction.

7. The semiconductor wafer of claim 1 , wherein the semiconductor substrate is a high resistivity substrate having a resistance in a range from 1000 ohm/centimeter to 100,000 ohm/centimeter.

8. A semiconductor wafer comprising:

a semiconductor substrate having a first substrate surface and a second substrate surface;

a plurality of first through substrate vias extending between the first and second substrate surfaces, wherein the plurality of first through substrate vias includes a first subset of one or more trench vias each having a primary axis aligned in a first direction, and a second subset of one or more trench vias each having a primary axis aligned in a second direction that is different from the first direction, and the plurality of first through substrate vias form an alignment pattern in an alignment area of the substrate;

a second through substrate via extending between the first and second substrate surfaces in a device area of the substrate;

a conductive layer directly connected to the second substrate surface and to first ends of the plurality of first through substrate vias, wherein the conductive layer is patterned so that a first portion of the conductive layer is directly coupled to the plurality of first through substrate vias, and a second portion of the conductive layer is directly coupled to the second through substrate via, and wherein a conductive material void is present, at the second substrate surface, in the conductive layer;

a transistor formed at the first substrate surface, wherein the second through substrate via is electrically coupled to the transistor; and

an inductor formed at the first substrate surface, and electrically coupled to the transistor, wherein the inductor is aligned with the conductive material void.

9. A semiconductor wafer comprising:

a semiconductor substrate having a first substrate surface and a second substrate surface;

a plurality of build up layers on the first substrate surface, wherein the plurality of build up layers include conductive layers and conductive vias;

a plurality of first through substrate vias extending between the first and second substrate surfaces, wherein the plurality of first through substrate vias includes a first subset of one or more trench vias each having a primary axis aligned in a first direction, and a second subset of one or more trench vias each having a primary axis aligned in a second direction that is different from the first direction, and the plurality of first through substrate vias form an alignment pattern in an alignment area of the substrate;

a semiconductor device formed at the first substrate surface, wherein the semiconductor device includes a plurality of terminals that are electrically coupled to the conductive layers and the conductive vias of the plurality of build up layers;

a second through substrate via extending between the first and second substrate surfaces, wherein the second through substrate via is electrically coupled to at least one of the plurality of terminals of the semiconductor device; and

a patterned conductive layer directly connected to the second substrate surface, wherein the patterned conductive layer includes a first portion directly coupled to first ends of the plurality of first through substrate vias, and a second portion directly coupled to a first end of the second through substrate via, and wherein a conductive material void is present, at the second substrate surface, in the patterned conductive layer.

10. The semiconductor wafer of claim 9 , wherein the first direction is orthogonal to the second direction.

11. A semiconductor wafer comprising:

a semiconductor substrate having a first substrate surface and a second substrate surface;

a plurality of first through substrate vias extending between the first and second substrate surfaces, wherein the plurality of first through substrate vias includes a first subset of one or more trench vias each having a primary axis aligned in a first direction, and a second subset of one or more trench vias each having a primary axis aligned in a second direction that is different from the first direction, and the plurality of first through substrate vias form an alignment pattern in an alignment area of the substrate;

a semiconductor device formed at the first substrate surface, wherein the semiconductor device includes a plurality of terminals;

an inductor formed at the first substrate surface, and electrically coupled to at least one of the plurality of terminals of the semiconductor device;

a second through substrate via extending between the first and second substrate surfaces, wherein the second through substrate via is electrically coupled to at least one of the plurality of terminals of the semiconductor device; and

a patterned conductive layer directly connected to the second substrate surface, to first ends of the plurality of first through substrate vias, and to a first end of the second through substrate via, and wherein the patterned conductive layer includes a conductive material void that is aligned with the inductor.

12. A method of fabricating a semiconductor wafer comprising:

forming a plurality of first through substrate vias through a semiconductor substrate that has a first substrate surface and a second substrate surface, wherein the plurality of first through substrate vias includes a first subset of one or more trench vias each having a primary axis aligned in a first direction, and a second subset of one or more trench vias each having a primary axis aligned in a second direction that is different from the first direction, and the plurality of first through substrate vias form an alignment pattern in an alignment area of the substrate;

forming a second through substrate via extending between the first and second substrate surfaces in a device area of the substrate;

forming a plurality of build up layers on the first substrate surface, wherein the plurality of build up layers include conductive layers and conductive vias that are electrically coupled to device terminals that are located over the first substrate surface in the device area of the substrate; and

forming a conductive layer directly on the second substrate surface and directly connected to first ends of the plurality of first through substrate vias; and

patterning the conductive layer so that a first portion of the conductive layer is directly coupled to the plurality of first through substrate vias, and a second portion of the conductive layer is directly coupled to the second through substrate via, and wherein a conductive material void is present, at the second substrate surface, in the conductive layer.

13. The method of claim 12 , wherein forming the conductive layer comprises:

forming a seed metal layer directly on the second substrate surface; and

forming a thick metal layer on the seed layer.

14. The method of claim 12 , further comprising:

forming a transistor at the first substrate surface, wherein the transistor includes a control terminal, a first current carrying terminal, and a second current carrying terminal, and wherein the second through substrate via is electrically coupled to the first current carrying terminal of the transistor.

15. The method of claim 12 , further comprising:

forming a transistor at the first substrate surface;

forming an inductor at the first substrate surface; and

electrically coupling the inductor to a terminal of the transistor, wherein the inductor is aligned with the conductive material void.

16. The method of claim 12 , wherein the first ends of the plurality of first through substrate vias have relative positions with respect to the second substrate surface that are selected from a position that is slightly recessed from the second substrate surface, a position that is slightly above the second substrate surface, and a position that is substantially co-planar with the second substrate surface.

17. The method of claim 12 , wherein the first direction is orthogonal to the second direction.