Programmable battery protection system and related methods
View Patent ↗A programmable battery protection system. Implementations may include a battery protection integrated circuit (IC) with an array of fuses, a plurality of latches coupled with the array of fuses, a plurality of MOSFETs coupled with the plurality of latches, and a plurality of resistors coupled in series and in parallel with each one of the plurality of MOSFETs. The IC may also include a comparator coupled with the plurality of resistors and with a battery control circuit. Whether any one of the array of fuses is open or closed (remains closed) may be set by a fuse trimming signal from the battery control circuit. A voltage supplied to the comparator by the plurality of resistors during operation may be one of a discharge overcurrent threshold voltage, a charge overcurrent threshold voltage, or a short current threshold voltage.
1. A programmable battery protection system comprising:
a battery;
only two field effect transistors (FETs) coupled with the battery, where at least one of the FETs is configured for use during charging of the battery (charging FET) and at least one of the FETs is configured for use during discharging of the battery (discharging FET);
a battery protection integrated circuit (IC) coupled with the charging FET and with the discharging FET wherein the battery protection IC comprises:
an array of fuses;
a plurality of latches coupled with the array of fuses;
a plurality of metal oxide semiconductor field effect transistors (MOSFETs) coupled with the plurality of latches;
a plurality of resistors coupled in series, each one of the plurality of resistors coupled in parallel with each one of the plurality of MOSFETs; and
a comparator coupled with the plurality of resistors and with a battery control circuit;
wherein whether any one of the array of the fuses is open or closed is set by a fuse trimming signal from the battery control circuit;
wherein the fuse trimming signal is a function of the on resistance of one of the charging FET, the discharging FET, and both the charging FET and discharging FET; and
wherein a voltage supplied to the comparator by the plurality of resistors during operation is one of a discharge overcurrent threshold voltage, a charge overcurrent threshold voltage, and a short current threshold voltage.
2. The system of claim 1 , wherein the battery protection IC is physically comprised in a same semiconductor package as the charging FET and the discharging FET.
3. The system of claim 2 , wherein the charging FET and the discharging FET are comprised on the same semiconductor chip.
4. The system of claim 1 , wherein the plurality of MOSFETs are p-channel MOSFETs.
5. The system of claim 1 , wherein the plurality of latches are gated D-latches.
6. The system of claim 1 , wherein the array of fuses are polyfuses comprising polysilicon.
7. The system of claim 1 , wherein the array of fuses are a Programmable Read Only Memory (PROM).
8. The system of claim 1 , wherein the array of fuses are a One-Time Programmable (OTP) memory.
9. A battery protection integrated circuit (IC) comprising:
an array of fuses;
a plurality of latches coupled with the array of fuses;
a plurality of metal oxide semiconductor field effect transistors (MOSFETs) coupled with the plurality of latches;
a plurality of resistors coupled in series, each one of the plurality of resistors coupled in parallel with each one of the plurality of MOSFETs; and
a comparator coupled with the plurality of resistors and with a battery control circuit;
wherein whether any one of the array of the fuses is open or closed is set by a fuse trimming signal from the battery control circuit;
wherein a voltage supplied to the comparator by the plurality of resistors during operation is one of a discharge overcurrent threshold voltage, a charge overcurrent threshold voltage, and a short current threshold voltage; and
wherein the battery control circuit is configured to be coupled with a battery and only two field effect transistors (FETs).
10. The IC of claim 9 , wherein the only two FETs further comprise wherein at least one of the FETs is configured for use during charging of a battery (charging FET) and at least one of the FETs is configured for use during discharging of the battery (discharging FET).
11. The IC of claim 10 , wherein the battery protection IC is physically comprised in a same semiconductor package as the charging FET and the discharging FET.
12. The IC of claim 11 , wherein the charging FET and the discharging FET are comprised on the same semiconductor chip.
13. The IC of claim 9 , wherein the plurality of MOSFETs are p-channel MOSFETs.
14. The IC of claim 9 , wherein the plurality of latches are gated D-latches.
15. The IC of claim 9 , wherein the array of fuses are polyfuses comprising polysilicon.
16. The IC of claim 9 , wherein the array of fuses are a Programmable Read Only Memory (PROM).
17. The IC of claim 9 , wherein the array of fuses are a One-Time Programmable (OTP) memory.