BULEX contacts in advanced FDSOI techniques
The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.
1. A method of forming a semiconductor device, the method comprising:
providing a silicon-on-insulator (SOI) substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material;
forming a gate structure above said active semiconductor layer in an active region of said SOI substrate;
forming a first opening in said active semiconductor layer and said buried insulating layer to partially expose said base substrate for forming a first bulk exposed region after said gate structure is formed; and
forming a contact structure in said first opening for contacting said first bulk exposed region.
2. The method of claim 1 , further comprising performing a well implantation process for implanting dopants into said first bulk exposed region for forming a first bulk well region prior to forming said contact structure.
3. The method of claim 2 , the method further comprising:
forming a shallow trench isolation (STI) structure in said SOI substrate prior to forming said gate structure; and
forming a second opening in said active semiconductor layer and said buried insulating layer to partially expose said base substrate for forming a second bulk exposed region, wherein said first and second bulk exposed regions and said active region are separated by said STI structure.
4. The method of claim 3 , wherein said first and second bulk exposed regions define a diode structure.
5. The method of claim 2 , wherein said first bulk exposed region is provided in said active region, and the method further comprises forming a silicide contact in said first bulk well region, said silicide contact being subsequently contacted by said contact structure for forming a back bias contact for said gate structure.
6. The method of claim 5 , further comprising forming raised source/drain (RSD) regions adjacent to said gate structure above said active region before exposing said base substrate, wherein said first opening is formed by etching a trench into said RSD regions at one side of said gate structure so as to expose said bulk substrate in said trench.
7. The method of claim 1 , further comprising implanting germanium into said active semiconductor layer of said active region for forming a silicon-germanium (SiGe) region in said active semiconductor layer prior to forming said gate structure.
8. The method of claim 1 , wherein forming said first opening comprises etching a trench into said active semiconductor layer and said buried insulating material layer.
9. The method of claim 8 , wherein forming said contact structure comprises forming a plasma-enhanced nitride (PEN) liner in said trench and depositing a contact material in said trench in alignment with said PEN liner.
10. The method of claim 9 , further comprising forming a silicide region in said bulk exposed region prior to forming said PEN liner.
11. A method of forming a semiconductor device, the method comprising:
providing a silicon-on-insulator (SOI) substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material;
forming a shallow trench isolation (STI) structure separating a first SOI region and a second SOI region;
forming a gate structure above said active semiconductor layer in said first SOI region;
partially exposing said bulk substrate in said first SOI region at one side of said gate structure and contacting said exposed bulk region in said first SOI region for forming a back bias contact for said gate structure in said first SOI region; and
forming a diode structure in said second SOI region after said gate structure is formed.
12. The method of claim 11 , wherein forming said diode structure comprises etching a first trench and a second trench into said second SOI region, each trench exposing said base substrate such that a first bulk exposed region and a second bulk exposed region are formed in said second SOI region, implanting a first well region having a first conductivity type into said first bulk exposed region, implanting a second well region having a second conductivity type opposite said first conductivity type, and forming a contact structure contacting said bulk well regions.
13. The method of claim 11 , further comprising forming a raised source/drain (RSD) region at both sides of said gate structure prior to forming said bulk exposed regions in said first and second SOI regions, and partially removing said RSD region at said one side of said gate structure when forming said exposed bulk region in said first region.
14. The method of claim 11 , wherein partially removing said RSD region comprises etching a trench into said RSD region at said one side of said gate structure, followed by forming a plasma-enhanced nitride (PEN) liner in said trench and depositing a contact material in said trench in alignment with said PEN liner for forming a back bias contact in said trench.
15. The method of claim 11 , further comprising implanting germanium into said active semiconductor layer of said first SOI region prior to forming said gate structure.
16. A method of forming a semiconductor device, the method comprising:
providing a silicon-on-insulator (SOI) substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material;
forming a shallow trench isolation (STI) structure separating a first SOI region and a second SOI region;
forming a gate structure above said active semiconductor layer in said first SOI region;
forming a raised source/drain (RSD) region at both sides of said gate structure on said first SOI region;
partially removing said RSD region on one side of said gate structure when forming said exposed bulk region in said first region; and
partially exposing said bulk substrate in said first SOI region at said one side of said gate structure after partially removing said RSD region and contacting said exposed bulk region in said first SOI region for forming a back bias contact for said gate structure in said first SOI region.
17. The method of claim 16 , wherein partially removing said RSD region comprises etching a trench into said RSD region at said one side of said gate structure, followed by forming a plasma-enhanced nitride (PEN) liner in said trench and depositing a contact material in said trench in alignment with said PEN liner for forming a back bias contact in said trench.
18. The method of claim 16 , wherein a diode structure is formed in said second SOI region by etching a first trench and a second trench into said second SOI region, each trench exposing said base substrate such that a first bulk exposed region and a second bulk exposed region are provided in said second SOI region, implanting well regions into said first and second bulk exposed regions for forming bulk well regions having opposite conductivity types, and forming a contact structure contacting said bulk well regions.