Self-aligned local interconnect technology

1. A self-aligned interconnect structure, comprising:

a fin structure patterned in a substrate;

an epitaxial contact disposed over the fin structure;

a first metal gate arranged adjacent to a second metal gate, the first metal gate and the second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and

an interconnect structure laterally connecting the first metal gate to the second metal gate;

wherein the interconnect structure is arranged between the first metal gate and the second metal gate and directly contacts the substrate.

2. The self-aligned interconnect structure of claim 1 , further comprising a silicon nitride (SiN) liner disposed over a portion of the epitaxial contact between the first metal gate and the second metal gate.

3. The self-aligned interconnect structure of claim 2 , wherein the SiN liner has a thickness in a range from about 2 to about 12 nanometers (nm).

4. The self-aligned interconnect structure of claim 1 , wherein the first and second metal gates comprise a high-k oxide layer, a work function metal, and a metal gate material.

5. The self-aligned interconnect structure of claim 4 , wherein the metal gate material is tungsten, tungsten titanium nitride, titanium, titanium nitride, tantalum, molybdenum, or any combination thereof.

6. The self-aligned interconnect structure of claim 1 , further comprising a SiN cap disposed over the interconnect structure.

7. The self-aligned interconnect structure of claim 1 , wherein the epitaxial contact comprises silicon, p-type dopants, n-type dopants, or any combination thereof.

8. The self-aligned interconnect structure of claim 1 , wherein the substrate comprises silicon or silicon germanium.

9. A method for making a self-aligned interconnect structure, the method comprising:

patterning a fin structure in a substrate;

growing an epitaxial contact over the fin structure by an epitaxial growth process;

forming a first gate and a second gate over and substantially perpendicular to the epitaxial contact, the first gate and the second gate being substantially parallel to one another;

patterning an interconnect structure in a region between the first gate and the second gate such that the interconnect structure pattern laterally connects the first gate and the second gate; and

filling the interconnect structure pattern, the first gate, and the second gate with a gate metal to form an interconnect structure that laterally connects the first gate and the second gate and directly contacts the substrate.

10. The method of claim 9 , wherein the first gate and the second gate comprise amorphous silicon before patterning the contact.

11. The method of claim 9 , wherein an inter-layer dielectric layer (ILD) layer surrounds the epitaxial contact.

12. The method of claim 11 , further comprising performing a lateral etching process to expose a portion of the epitaxial contact.

13. The method of claim 12 , further comprising depositing a SiN liner over a portion of the epitaxial contact.

14. The method of claim 9 , further comprising filling the interconnect structure with amorphous silicon and removing the amorphous silicon before filling with a gate metal.

15. A method for making a self-aligned interconnect structure, the method comprising:

patterning a fin structure in a substrate;

growing an epitaxial contact over the fin structure by an epitaxial growth process;

forming a first gate and a second gate over and substantially perpendicular to the epitaxial contact, the first gate and the second gate being substantially parallel to one another and comprising amorphous silicon;

patterning and etching through an inter-layer dielectric layer (ILD) between the first and second gates to form an interconnect structure pattern that laterally connects the first gate to the second gate;

removing the amorphous silicon from the first gate and the second gate after patterning and etching the ILD; and

filling the interconnect structure pattern, the first gate, and the second gate with a gate metal to form an interconnect structure that laterally connects the first gate and the second gate and directly contacts the substrate.

16. The method of claim 15 , further comprising depositing a high-k oxide and a high work function metal before filling with the gate metal.

17. The method of claim 15 , further comprising forming a SiN cap over the contact after filling with the gate metal.

18. The method of claim 15 , wherein the epitaxial contact comprises silicon, p-type dopants n-type dopants, or any combination thereof.

19. The method of claim 15 , wherein the substrate comprises silicon or silicon germanium.