Method of selectively depositing floating gate material in a memory device
Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material.
1. A method of making a NAND memory device comprising a semiconductor channel and a plurality of control gate electrodes, the method comprising selectively forming metal floating gate material on a second dielectric material surface having a lesser hydrophobicity than a first dielectric material surface;
further comprising:
providing patterned surfaces over a substrate, the patterned surfaces comprising the first dielectric material surface and the second dielectric material surface having the lesser hydrophobicity than the first dielectric material surface;
performing a selective metal deposition process that deposits the metal floating gate material at a higher nucleation density on the second dielectric material surface than on the first dielectric material surface; and
depositing a blocking dielectric and the plurality of control gate electrodes over the metal floating gate material.
2. A method of making a NAND memory device comprising a semiconductor channel and a plurality of control gate electrodes, the method comprising selectively forming metal floating gate material on a second dielectric material surface having a lesser hydrophobicity than a first dielectric material surface;
wherein the floating gate metal material is deposited as a metal material portion on the second dielectric material surface and as isolated islands of the metal material on the first dielectric material surface that do not cover more than 1% of the first dielectric material surface.
3. The method of claim 2 , wherein:
the isolated islands of the metal material do not physically contact one another, and do not form an electrically conductive path;
the first dielectric material comprises a silicon oxide tunnel dielectric;
the second dielectric material comprises a silicon nitride charge trapping dielectric; and
the metal material comprises ruthenium deposited employing an atomic layer deposition process.
4. The method of claim 3 , wherein the atomic layer deposition process employs RuO 4 as a precursor gas, and the ruthenium is deposited by reduction of adsorbed molecules of RuO 4 .
5. The method of claim 3 , further comprising forming a polysilicon floating gate between the tunnel dielectric and the silicon nitride charge trapping dielectric to form a hybrid charge storage region comprising the polysilicon floating gate, the silicon nitride charge trapping dielectric and the ruthenium capping layer.
6. The method of claim 5 , wherein the first dielectric material surface further comprises surfaces of silicon oxide shallow trench isolation regions exposed between stacks comprising the polysilicon floating gate and the silicon nitride charge trapping dielectric.
7. The method of claim 2 , further comprising:
providing patterned surfaces over a substrate, the patterned surfaces comprising the first dielectric material surface and the second dielectric material surface having the lesser hydrophobicity than the first dielectric material surface;
performing a selective metal deposition process that deposits the metal floating gate material at a higher nucleation density on the second dielectric material surface than on the first dielectric material surface; and
depositing a blocking dielectric and the plurality of control gate electrodes over the metal floating gate material.