Continuous adaptive data capture optimization for interface circuits
View Patent ↗A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0.
1. A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation, comprising;
receiving a first stream of data bits input to the data interface circuit;
initially establishing, using a first calibration method, an optimal sampling point for sampling the data bits input to the data interface circuit;
receiving a second stream of data bits input to the data interface circuit during normal system operation;
from time to time during normal system operation, and without disturbing normal system operation, performing a second calibration method different from the first, the second calibration method comprising:
establishing at least one reference data path for sampling transition edges of the second stream of data bits input to the data interface during normal system operation;
using the at least one reference data path, sampling a plurality of fringe timing points associated with transition edges of the second stream of data bits input to the data interface circuit; wherein the sampling the fringe timing points associated with the transition edge of a particular data bit comprises sampling: a) a plurality of interfringe timing points; and b) an intrafringe timing point;
comparing a first fringe timing measurement made during a first performance of the second calibration method, with a second fringe timing measurement made during a second performance of the second calibration method to determine a drift amount for transition edges of the second stream of data bits input to the data interface;
comparing the drift amount with a drift correction threshold value; and
if the drift amount is greater than the drift correction threshold value, shifting the first optimal timing point in time by the drift amount to revise the first optimal sampling point.
2. The method of claim 1 wherein for the second calibration method the transition edges of the data bits may be rising edge transitions and/or falling edge transitions, and may be associated with any random data bit pattern.
3. The method of claim 1 wherein for the first calibration method a known and predictable data pattern is input to the data interface circuit; and
wherein for the second calibration method an unknown and unpredictable data bit pattern is input to the data interface circuit.
4. The method of claim 1 wherein multiple daisy-chained delay lines are used in construction of the data interface circuit, and wherein each of the multiple delay lines is constructed such that a duty cycle of a signal entering the delay line is the same as the duty cycle of a delayed version of the same signal when it exits the delay line.
5. A method for operating a data interface circuit whereby calibration adjustments are frequently made during normal system operation and without disturbing normal system operation, comprising;
initially establishing, using a first calibration method, an optimal sampling point for sampling data bits received by an input of the data interface circuit;
from time to time during system operation, and without disturbing normal system operation, performing a second calibration method that is different from the first, the second calibration method comprising:
sampling transition edges of data bits received by the input, wherein values of the received data bits represent a random pattern from perspective of the data interface circuit; wherein for the second calibration method sampling the fringe timing points associated with the transition edge of a data bit comprises sampling: a) a plurality of interfringe timing points; and b) an intrafringe timing point;
determining that the transition edges have drifted relative to the optimal sampling point by a drift delay amount, the drift having occurred since a previous creation or adjustment of the optimal sampling point;
adjusting the optimal sampling point by adding or subtracting the drift delay amount from, or adding the drift delay amount to, the optimal sampling point to create a revised optimal sampling point; and
wherein the first calibration method requires a specific data pattern to be provided to the input of the data interface circuit, and the second calibration method operates successfully on any random pattern of data bit values provided to the input of the data interface circuit.
6. The method of claim 5 wherein for the second calibration method the transition edges of data bits may be rising edge transitions and/or falling edge transitions, and may be associated with any random data bit pattern.
7. The method of claim 5 wherein for the first calibration method a known and predictable data pattern is input to the data interface circuit; and
wherein for the second calibration method an unknown and unpredictable data bit pattern is input to the data interface circuit.
8. The method of claim 5 wherein multiple daisy-chained delay lines are used in construction of the data interface circuit, and where each of the multiple delay lines is constructed such that a duty cycle of a signal entering the delay line is the same as the duty cycle of a delayed version of the same signal when it exits the delay line.
9. A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation, comprising;
initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is known and predictable, an optimal sampling point for sampling data bits received by the data interface circuit;
during normal system operation and without disturbing normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unknown and unpredictable, and wherein the second calibration method determines an amount of timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point;
wherein from time to time during system operation, and without disturbing normal system operation, performing the second calibration method where the data bit pattern received by the data interface circuit is unknown and unpredictable, and wherein the second calibration method determines an amount of timing drift for received data bit edge transitions and adjusts the revised optimal timing point to create a new revised optimal timing point; wherein for the second calibration method sampling the fringe timing points associated with the transition edge of a data bit comprises sampling: a) a plurality of interfringe timing points; and b) an intrafringe timing point.
10. The method of claim 9 wherein for the second calibration method the data bit pattern transition edges may be rising edge transitions or falling edge transitions, and may be associated with any random data bit pattern.
11. The method of claim 9 wherein multiple daisy-chained delay lines are used in construction of the data interface circuit, and where each of the multiple delay lines is constructed such that a duty cycle of a signal entering the delay line is the same as the duty cycle of a delayed version of the same signal when it exits the delay line.