Ultrathin semiconductor channel three-dimensional memory devices
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects.
1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate; and
memory stack structures extending through the alternating stack, wherein:
each memory stack structure comprises a semiconductor channel doped with argon.
2. The three-dimensional memory device of claim 1 , wherein an atomic concentration of argon in the semiconductor channel is in a range from 1.0×10 17 /cm 3 to 5.0×10 20 /cm 3 .
3. The three-dimensional memory device of claim 1 , wherein the semiconductor channel is further doped with deuterium atoms.
4. The three-dimensional memory device of claim 3 , wherein an atomic concentration of deuterium atoms in the semiconductor channel is in a range from 1.0×10 17 /cm 3 to 5.0×10 20 /cm 3 .
5. The three-dimensional memory device of claim 1 , wherein the semiconductor channel comprises at least one of:
(a) the semiconductor channel has a thickness not greater than 5.0 nm and a first sidewall having a surface roughness not greater than 10% of the thickness of the semiconductor channel; or
(b) the semiconductor channel has the surface roughness less than 0.5 nm in root mean square thickness.
6. The three-dimensional memory device of claim 5 , wherein:
a second sidewall of the semiconductor channel has a surface roughness not greater than 10% of the thickness of the semiconductor channel;
one of the first sidewall and the second sidewall is an inner sidewall; and
another of the first sidewall and the second sidewall is an outer sidewall.
7. The three-dimensional memory device of claim 1 , wherein a sidewall of the semiconductor channel is in physical contact with an aluminum oxide layer.
8. The three-dimensional memory device of claim 7 , wherein:
the aluminum oxide layer laterally surrounds, and contacts a sidewall of, a dielectric core; and
an outer sidewall of the semiconductor channel is in physical contact with a dielectric interface layer comprising a material selected from silicon oxide and aluminum oxide.
9. The three-dimensional memory device of claim 7 , wherein the aluminum oxide layer is an innermost layer of a tunneling dielectric that laterally surrounds the semiconductor channel.
10. The three-dimensional memory device of claim 1 , wherein:
each semiconductor channel contacts an outer sidewall of a dielectric interface layer;
an inner sidewall of the dielectric interface layer contacts a sidewall of a dielectric core; and
the dielectric interface layer comprises a material selected from thermal silicon oxide and aluminum oxide.
11. The three-dimensional memory device of claim 1 , wherein the semiconductor channel has an interface trap density that is not greater than 1.0×10 12 /cm 2 .
12. The three-dimensional memory device of claim 1 , wherein each of the memory stack structures comprises, from inside to outside:
a respective semiconductor channel;
a tunneling dielectric laterally surrounding the respective semiconductor channel; and
charge storage regions laterally surrounding the tunneling dielectric.
13. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a device region;
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrodes and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.
14. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate; and
memory stack structures extending through the alternating stack,
wherein each memory stack structure comprises a semiconductor channel having at least one of:
(a) a thickness not greater than 5.0 nm and a first sidewall having a surface roughness not greater than 10% of the thickness of the semiconductor channel; or
(b) the surface roughness less than 0.5 nm in root mean square thickness and;
wherein each memory stack structure comprises the semiconductor channel doped with argon at an atomic concentration in a range from 1.0×10 17 /cm 3 to 5.0×10 20 /cm 3 .
15. The three-dimensional memory device of claim 14 , wherein:
the semiconductor channel has the thickness not greater than 5.0 nm and the first sidewall having the surface roughness not greater than 10% of the thickness of the semiconductor channel;
a second sidewall of the semiconductor channel has a surface roughness not greater than 10% of the thickness of the semiconductor channel;
one of the first sidewall and the second sidewall is an inner sidewall; and
another of the first sidewall and the second sidewall is an outer sidewall.
16. The three-dimensional memory device of claim 14 , wherein a sidewall of the semiconductor channel is in physical contact with an aluminum oxide layer and wherein the surface roughness of the semiconductor channel is less than 0.5 nm in root mean square thickness.
17. The three-dimensional memory device of claim 16 , wherein:
the aluminum oxide layer laterally surrounds, and contacts a sidewall of, a dielectric core; and
an outer sidewall of the semiconductor channel is in physical contact with a dielectric interface layer comprising a material selected from silicon oxide and aluminum oxide.
18. The three-dimensional memory device of claim 16 , wherein the aluminum oxide layer is an innermost layer of a tunneling dielectric that laterally surrounds the semiconductor channel.
19. The three-dimensional memory device of claim 14 , wherein the semiconductor channel is further doped with deuterium atoms at an atomic concentration in a range from 1.0×10 17 /cm 3 to 5.0×10 20 /cm 3 .
20. The three-dimensional memory device of claim 14 , wherein:
each semiconductor channel contacts an outer sidewall of a dielectric interface layer; and
an inner sidewall of the dielectric interface layer contacts a sidewall of a dielectric core; and
the dielectric interface layer comprises a material selected from thermal silicon oxide and aluminum oxide.
21. The three-dimensional memory device of claim 14 , wherein each of the memory stack structures comprises, from inside to outside:
a respective semiconductor channel;
a tunneling dielectric laterally surrounding the respective semiconductor channel; and
charge storage regions laterally surrounding the tunneling dielectric.
22. The three-dimensional memory device of claim 14 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a device region;
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.
23. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate; and
memory stack structures extending through the alternating stack, wherein:
each memory stack structure comprises a semiconductor channel including an inner sidewall in physical contact with an outer sidewall of an aluminum oxide layer;
each memory stack structure comprises the semiconductor channel doped with argon at an atomic concentration in a range from 1.0×10 17 /cm 3 to 5.0×10 20 /cm 3 ; and
the semiconductor channel is further doped with deuterium atoms at an atomic concentration in a range from 1.0×10 17 /cm 3 to 5.0×10 20 /cm 3 .
24. The three-dimensional memory device of claim 23 , wherein:
the aluminum oxide layer laterally surrounds, and contacts a sidewall of, a dielectric core.
25. The three-dimensional memory device of claim 23 , wherein an outer sidewall of the semiconductor channel is in physical contact with a dielectric interface layer comprising a material selected from silicon oxide and aluminum oxide.
26. The three-dimensional memory device of claim 23 , wherein:
the semiconductor channel has a thickness not greater than 5.0 nm;
an inner sidewall of the semiconductor channel has a surface roughness not greater than 10% of the thickness of the semiconductor channel; and
an outer sidewall of the semiconductor channel has a surface roughness not greater than 10% of the thickness of the semiconductor channel.
27. The three-dimensional memory device of claim 23 , wherein:
each semiconductor channel contacts an outer sidewall of a dielectric interface layer;
an inner sidewall of the dielectric interface layer contacts a sidewall of a dielectric core; and
the dielectric interface layer comprises a material selected from thermal silicon oxide and aluminum oxide.
28. The three-dimensional memory device of claim 23 , wherein the semiconductor channel has an interface trap density that is not greater than 1.0×10 12 /cm 2 .
29. The three-dimensional memory device of claim 23 , wherein each of the memory stack structures comprises, from inside to outside:
a respective semiconductor channel;
a tunneling dielectric laterally surrounding the respective semiconductor channel; and
charge storage regions laterally surrounding the tunneling dielectric.
30. The three-dimensional memory device of claim 23 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a device region;
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.
31. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate; and
memory stack structures extending through the alternating stack; wherein:
each memory stack structure comprises a semiconductor channel;
a sidewall of the semiconductor channel is in physical contact with an aluminum oxide layer; and
a surface roughness of the semiconductor channel is less than 0.5 nm in root mean square thickness.
32. The three-dimensional memory device of claim 31 , wherein:
the aluminum oxide layer laterally surrounds, and contacts a sidewall of, a dielectric core; and
an outer sidewall of the semiconductor channel is in physical contact with a dielectric interface layer comprising a material selected from silicon oxide and aluminum oxide.
33. The three-dimensional memory device of claim 31 , wherein the aluminum oxide layer is an innermost layer of a tunneling dielectric that laterally surrounds the semiconductor channel.