Three-dimensional memory devices having a shaped epitaxial channel portion
View Patent ↗An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.
1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a memory opening extending through the alternating stack;
an epitaxial channel portion located at a bottom of the memory opening and contacting a portion of the substrate;
a memory stack structure overlying the epitaxial channel portion and located in the memory opening; and
a dielectric collar structure laterally surrounding at least the epitaxial channel portion and having a first thickness region having a first thickness and a second thickness region having a second thickness that is greater than the first thickness, the second thickness region being located at a level of one of the electrically conductive layers and contacting an outer sidewall of the epitaxial channel portion.
2. The three-dimensional memory device of claim 1 , wherein an outer sidewall of the second thickness region protrudes outward from a vertical plane including an outer sidewall of the first thickness region.
3. The three-dimensional memory device of claim 2 , wherein an inner sidewall of the first thickness region is recessed inward from a vertical plane including an inner sidewall of the second thickness region.
4. The three-dimensional memory device of claim 2 , wherein an inner sidewall of the second thickness region is located within a same vertical plane as an inner sidewall of the first thickness region.
5. The three-dimensional memory device of claim 1 , wherein:
an outer sidewall of the first thickness region contacts a sidewall of a semiconductor material layer in the substrate; and
an inner sidewall of the first thickness region contacts a sidewall of the epitaxial channel portion.
6. The three-dimensional memory device of claim 5 , wherein the first thickness region underlies the second thickness region.
7. The three-dimensional memory device of claim 1 , wherein the memory stack structure comprises a blocking dielectric contacting a sidewall of the memory opening, contacting a top surface of the epitaxial channel portion, and having an outer sidewall that is vertically coincident with an outer sidewall of the first thickness region.
8. The three-dimensional memory device of claim 1 , wherein a bottom surface of the dielectric collar structure overlies a topmost surface of the substrate.
9. The three-dimensional memory device of claim 8 , wherein the first thickness region overlies the second thickness region.
10. The three-dimensional memory device of claim 1 , wherein the memory stack structure comprises a blocking dielectric contacting an inner sidewall of the first thickness region and contacting a top surface of the epitaxial channel portion.
11. The three-dimensional memory device of claim 1 , wherein each of the memory stack structures comprises, from inside to outside:
a semiconductor channel;
a tunneling dielectric laterally surrounding the semiconductor channel; and
charge storage regions laterally surrounding the tunneling dielectric.
12. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a device region;
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.