Gate structures for III-N devices
A semiconductor device includes a III-N layer, a plurality of parallel conductive fingers on the III-N layer, an insulator layer over the III-N layer, and a gate. The plurality of parallel conductive fingers includes a source and drain bus, a plurality of source fingers coupled to the source bus and extending from the source bus towards the drain bus to respective source finger ends, and a plurality of drain fingers coupled to the drain bus and extending from the drain bus towards the source bus to respective drain finger ends, the drain fingers being interdigitated between the source fingers. The gate comprises a plurality of straight and a plurality of connecting sections, each straight section between a source finger and adjacent drain finger, and the connecting sections each joining two adjacent straight sections and curving around a respective source or drain finger end.
1. A method of fabricating a semiconductor device, the method comprising:
forming a III-N layer on a substrate;
forming a plurality of parallel conductive fingers on the III-N layer, including forming:
a source bus and a drain bus;
a plurality of source fingers coupled to the source bus and extending from the source bus towards the drain bus to respective source finger ends; and
a plurality of drain fingers coupled to the drain bus and extending from the drain bus towards the source bus to respective drain finger ends, wherein the drain fingers are interdigitated between the source fingers;
forming an insulator layer over the III-N layer;
etching a gate recess in the insulator layer, the gate recess comprising:
a plurality of straight sections, each straight section lying between a source finger and an adjacent drain finger and having a substantially uniform length along a direction of current flow of the semiconductor device;
a plurality of connecting sections, each connecting section joining two adjacent straight sections at joining points, each connecting section including a first edge proximal to a respective source finger end or drain finger end and a second edge opposite the first edge, wherein a length of the connecting section, measured in a direction substantially perpendicular to the first and second edges, gradually expands from a value of the substantially uniform length of the two adjacent straight sections at the joining points to a larger value at one or more intermediary points between the joining points;
cleaning the gate recess using a chemical cleaning process; and
forming a gate over the gate recess.
2. The method of claim 1 , wherein each connecting section curves continuously around a respective source finger end or drain finger end.
3. The method of claim 1 , wherein forming the III-N layer comprises forming a III-N channel layer and a III-N barrier layer, wherein a compositional difference between the III-N channel layer and the III-N barrier layer causes a 2DEG channel to be induced in the III-N channel layer adjacent to the III-N barrier layer.
4. The method of claim 3 , comprising implanting ions into the III-N layer in one or more peripheral edge regions underneath the connecting sections of the gate recess, thereby causing the 2DEG channel not to be induced in the peripheral edge regions.
5. The method of claim 3 , wherein etching the gate recess comprises etching the gate recess, in one or more peripheral edge regions underneath the connecting sections of the gate recess, to a depth sufficient to cause the 2DEG channel not to be induced under the gate in the peripheral edge regions.
6. The method of claim 1 , wherein etching the gate recess comprises etching the gate recess to leave slanted sidewalls for the gate.
7. The method of claim 1 , wherein forming the insulator layer comprises forming a gate insulator layer over the III-N layer, an etch stop layer over the gate insulator layer, and an electrode defining layer over the etch stop layer.
8. The method of claim 7 , wherein etching the gate recess comprises etching the gate recess, in an active region underneath the straight sections, to a depth into the etch stop layer.
9. The method of claim 7 , wherein the gate insulator layer comprises silicon nitride, the etch stop layer comprises aluminum nitride, and the electrode defining layer comprises silicon nitride.
10. The method of claim 1 , wherein each connecting section is a curved section which curves around a respective source finger end or drain finger end.
11. A semiconductor device comprising:
a III-N layer;
a plurality of parallel conductive fingers on the III-N layer, including:
a source bus and a drain bus;
a plurality of source fingers coupled to the source bus and extending from the source bus towards the drain bus to respective source finger ends; and
a plurality of drain fingers coupled to the drain bus and extending from the drain bus towards the source bus to respective drain finger ends, wherein the drain fingers are interdigitated between the source fingers;
an insulator layer over the III-N layer; and
a gate comprising:
a plurality of straight sections, each straight section lying between a source finger and an adjacent drain finger and having a substantially uniform length along a direction of current flow of the semiconductor device; and
a plurality of connecting sections, each connecting section joining two adjacent straight sections at joining points, each connecting section including a first edge proximal to a respective source finger end or drain finger end and a second edge opposite the first edge, wherein a length of the connecting section, measured in a direction substantially perpendicular to the first and second edges, gradually expands from a value of the substantially uniform length of the two adjacent straight sections at the joining points to a larger value at one or more intermediary points between the joining points.
12. The semiconductor device of claim 11 , wherein each connecting section curves continuously around a respective source finger end or drain finger end.
13. The semiconductor device of claim 11 , wherein the III-N layer comprises a III-N channel layer and a III-N barrier layer, wherein a compositional difference between the III-N channel layer and the III-N barrier layer causes a 2DEG channel to be induced in the III-N channel layer adjacent to the III-N barrier layer.
14. The semiconductor device of claim 13 , wherein ions are implanted into one or more peripheral edge regions underneath the connecting sections of the gate, thereby causing the 2DEG channel not to be induced in the peripheral edge regions.
15. The semiconductor device of claim 13 , wherein the gate is recessed, in one or more peripheral edge regions underneath the connecting sections of the gate, to a depth sufficient to cause the 2DEG channel not to be induced under the connecting sections of the gate in the peripheral edge regions.
16. The semiconductor device of claim 11 , wherein the gate comprises slanted sidewalls.
17. The semiconductor device of claim 11 , further comprising a recess in the insulator layer, wherein the gate is in the recess.
18. The semiconductor device of claim 17 , wherein a length of a portion of the recess beneath the plurality of connecting sections is greater than a length of the recess in a direction of current flow beneath the plurality of straight sections.
19. The semiconductor device of claim 11 , wherein the insulator layer comprises a gate insulator layer over the III-N layer, an etch stop layer over the gate insulator layer, and an electrode defining layer over the etch stop layer.
20. The semiconductor device of claim 19 , wherein the gate is recessed, in an active region underneath the straight sections, to a depth into the etch stop layer.
21. The semiconductor device of claim 19 , wherein the gate insulator layer comprises silicon nitride, the etch stop layer comprises aluminum nitride, and the electrode defining layer comprises silicon nitride.
22. The semiconductor device of claim 11 , wherein each connecting section is a curved section which curves around a respective source finger end or drain finger end.