End of life prediction to reduce retention triggered operations
View Patent ↗A memory system or flash card includes a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects can be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements are used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements leads to improved memory management and data management. That action includes calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.
1. A method for predicting an end of life value of a memory comprising memory blocks, the method comprising:
analyzing individual ones of the memory blocks to determine a bit error rate slope which is a change of bit errors over time;
calculating an end of retention point based on an average of the bit error rate slope for each of the memory blocks, wherein the end of retention point is when the bit error rate equals a minimum error threshold; and
normalizing wear for the memory blocks so that the bit error rate slope for each of the blocks is directed towards the end of retention point.
2. The method of claim 1 wherein the normalizing comprises:
refreshing ones of the memory blocks based on a retention rate for each of the ones of the memory blocks.
3. The method of claim 2 wherein the retention rate is based on the bit error rate.
4. The method of claim 1 further comprising:
modifying an amount of usage of the memory blocks to account for the bit error rate of each of the blocks in order to extend the end of retention point for all of the blocks; and
modifying retention triggering operations based on the end of retention point.
5. The method of claim 4 further comprising:
determining a read disturb signature;
wherein the determining of the bit error rate is based on the read disturb signature.
6. The method of claim 5 wherein the read disturb signature influences the bit error rate slope.
7. The method of claim 4 wherein the retention triggering operations comprise block refreshment.
8. The method of claim 7 wherein the block refreshment comprises rewriting data.
9. A method for measuring wear comprising:
performing the following in a storage device comprising blocks of memory:
determining a read disturb;
modifying an amount of usage of the blocks to account for the read disturb of each of the blocks in order to extend an end of retention point for those blocks with higher read disturb, and to increase the amount of usage of those blocks with a lower read disturb; and
modifying retention triggering operations based on the end of retention point.
10. The method of claim 9 wherein the determining the read disturb further comprises:
measuring, periodically, voltage distribution of states for each cell in a memory;
calculating a width of the voltage distribution over a certain number of cycles; and
quantizing the read disturb based on changes to the width.
11. The method of claim 10 wherein the width of the voltage distribution comprises a signature of the read disturb.
12. The method of claim 9 wherein the width comprises a width of an error state of the voltage distribution.
13. The method of claim 9 wherein the width comprises a calculation of a standard deviation of the voltage distribution.
14. A storage device comprising a controller and memory blocks, wherein the processor is configured for:
calculating a bit error rate slope for each of the memory blocks, wherein the bit error rate slope comprises a change of bit errors over time;
determining an end of life point based on the bit error rate slope for each of the memory blocks, wherein the end of life point comprises an average time for the bit error rate slopes from the memory blocks to converge with a minimum error threshold; and
adjusting usage of the memory blocks based on the bit error rate slope such that the bit error rate slope for each of the memory blocks should be adjusted towards the end of life point.
15. The storage device of claim 14 , wherein the adjusting usage of the memory blocks comprises refreshing those memory blocks with a higher bit error rate in order to extend the bit error rate slope.
16. The storage device of claim 15 , wherein the adjusting usage of the memory blocks comprises those memory blocks with a lower bit error rate being used more frequently, while those memory blocks with a higher bit error rate are used less frequently in order to extend the bit error rate slope.
17. The storage device of claim 14 , wherein the adjusting usage of the memory blocks comprises normalizing wear of the memory blocks such that the bit error rate slopes of the memory blocks converges towards the end of life point.
18. The storage device of claim 17 , wherein wear usage is increased for blocks with a lowest bit error rate and bit error rate slopes that extend for a longer time.
19. The storage device of claim 14 , wherein the end of life point is not based on a worst case scenario of the memory block with a highest bit error rate and a bit error rate slope that reaches the end of life point quicker than other ones of the bit error rate slopes.
20. The storage device of claim 19 , wherein the average time is an average of all of the bit error slopes.