Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first voltage to a memory cell prior to an operation, wherein a magnitude of the first voltage is approximately 5 volts. The method further includes providing a second voltage to the memory cell during the operation, wherein a magnitude of the second voltage is in the range of approximately 1.0 and 1.5 volts. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.
1. A method comprising:
providing a first voltage to a memory cell prior to an operation, wherein a magnitude of the first voltage is approximately 5 volts;
providing a second voltage to the memory cell during the operation, wherein a magnitude of the second voltage is in the range of approximately 1.0 and 1.5 volts; and
determining a state of the memory cell after providing the first voltage and the second voltage.
2. The method of claim 1 , wherein the second voltage is applied longer than the first voltage is applied.
3. The method of claim 1 , wherein the operation is a read operation and wherein a magnitude of the second voltage is approximately 1.0 volt.
4. The method of claim 1 , wherein the operation is a verify operation and wherein a magnitude of the second voltage is approximately 1.5 volt.
5. The method of claim 1 , wherein determining the state comprises sensing a current across the memory cell.
6. The method of claim 1 , wherein determining the state comprises sensing a data line response.
7. The method of claim 1 , wherein determining the state comprises transferring an output voltage to an output pad and determining the output voltage on the output pad.
8. A method comprising:
providing a first voltage to a memory cell prior to an operation;
providing a second voltage to the memory cell during the operation, wherein a difference between a magnitude of the first voltage and a magnitude of the second voltage is in the range of approximately 3.0 and 3.5 volts; and
determining a state of the memory cell after providing the first voltage and the second voltage.
9. The method of claim 8 , wherein the first voltage is approximately 5 volts.
10. The method of claim 8 , wherein the magnitude of the first voltage is approximately 5 volts.
11. The method of claim 8 , wherein the second voltage is applied longer than the first voltage is applied.
12. The method of claim 8 , wherein the operation is a read operation and wherein the second voltage is approximately 1.0 volt.
13. The method of claim 8 , wherein the operation is a verify operation and wherein the second voltage is approximately 1.5 volt.
14. A method comprising:
applying an excited pulse to a control gate of a memory cell during a first time period, wherein the excited pulse comprises a first voltage level;
transitioning the excited pulse to a second voltage level during a second time period, wherein the second voltage level is read voltage; and
transitioning the excited pulse to a third voltage level before transitioning to the second voltage level.
15. The method of claim 14 , wherein the second time period is greater than the first time period.
16. The method of claim 14 , wherein transitioning to the third voltage level comprises transitioning to approximately 0 volts.
17. The method of claim 14 , wherein applying the excited pulse comprises applying a voltage having a magnitude of approximately 5 volts.
18. The method of claim 14 , wherein transitioning to the read level comprises transitioning to approximately 1.0 volts.
19. The method of claim 14 , comprising determining a state of the memory cell after transitioning the excited pulse to a read level.
20. A method comprising:
applying an excited pulse to a control gate of a memory cell during a first time period, wherein the excited pulse comprises a first voltage level; and
transitioning the excited pulse to a second voltage level during a second time period, wherein the second voltage level is read voltage, wherein the second time period is greater than the first time period.