FinFET low resistivity contact formation method

1. A semiconductor device comprising:

a fin on a substrate;

a gate electrode over the fin;

source/drain regions in the fin on opposing sides of the gate electrode, wherein the source/drain regions comprise a material having a lattice constant different from a lattice constant of the substrate, and wherein the source/drain regions comprise a passivated treatment layer;

an inter-layer dielectric (ILD) layer having an opening over the passivated treatment layer of the source/drain regions;

a conductive dielectric layer along sidewalls of the opening and a surface of the passivated treatment layer, wherein the conductive dielectric layer is formed of a dielectric material, and is configured to allow charges to pass through;

a metallic barrier over the conductive dielectric layer; and

a metal layer filling the opening in the ILD layer.

2. The semiconductor device of claim 1 , wherein metallic barrier comprises Ta, Zn, Sn, Cd, In, or Ru.

3. The semiconductor device of claim 2 , wherein the metallic barrier has a thickness between 0.5 nm and 3 nm.

4. The semiconductor device of claim 1 , further comprising a metal cap interface layer between the metallic barrier and conductive dielectric layer.

5. The semiconductor device of claim 1 , wherein the conductive dielectric layer comprises forming a thin layer of Al 2 O 3 .

6. The semiconductor device of claim 1 , wherein the passivated treatment layer has a thickness between 0.5 nm and 2 nm.

7. The semiconductor device of claim 1 , wherein the passivated treatment layer is free from metal.

8. A semiconductor device comprising:

a fin on a substrate;

a gate electrode over the fin;

source/drain regions in the fin on opposing sides of the gate electrode, wherein the source/drain regions comprise a material having a lattice constant different from a lattice constant of the substrate;

an inter-layer dielectric (ILD) layer over the source/drain regions; and

a contact structure extending through the ILD layer to the source/drain regions, the contact structure comprising:

a passivated layer on the source/drain regions; and

one or more conductive layers over the passivated layer, wherein the one or more conductive layers comprise a metal oxide layer.

9. The semiconductor device of claim 8 , wherein the passivated layer has a lower density of interface traps than the material, wherein the passivated layer comprises elements of the material.

10. The semiconductor device of claim 8 , wherein the contact structure further comprises

a conductive fill, wherein the metal oxide layer is interposed between the passivated layer and the conductive fill, and the metal oxide layer is formed of a dielectric material, and the metal oxide layer is configured to allow conduction of charges between the conductive fill and one of the source/drain regions.

11. The semiconductor device of claim 10 , wherein the one or more conductive layers comprises a metallic barrier interposed between the metal oxide layer and the conductive fill.

12. The semiconductor device of claim 11 , wherein the one or more conductive layers comprises a metal cap interface layer, the metal cap interface layer interposed between the metallic barrier and the metal oxide layer, the metal cap interface layer composed of a material comprising at least some elements present in the metallic barrier and at least some elements present in the conductive fill.

13. The semiconductor device of claim 10 , wherein the metal oxide layer comprises a thin layer of Al 2 O 3 .

14. The semiconductor device of claim 8 , wherein the one or more conductive layers comprises:

a metallic barrier; and

a conductive fill, wherein the metallic barrier is interposed between the passivated layer and the conductive fill.

15. The semiconductor device of claim 8 , wherein the passivated layer is free from metal.

16. A semiconductor device comprising:

a fin on a substrate;

a gate electrode over the fin;

a first source/drain region and a second source/drain region in the fin on opposing sides of the gate electrode, wherein the first source/drain region and the second source/drain region comprise an epitaxial material, the epitaxial material having a lattice constant different from a lattice constant of an immediately underlying material;

an inter-layer dielectric (ILD) layer over the gate electrode, the first source/drain region and the second source/drain region;

a conductive fill extending into the ILD and electrically coupled to the first source/drain region;

a passivated layer interposed between the epitaxial material and the conductive fill;

a conductive dielectric layer interposed between the conductive fill and the passivated layer, the conductive dielectric layer being interposed between the conductive fill and the ILD; and

a metallic barrier interposed between the conductive dielectric layer and the conductive fill, wherein the conductive dielectric layer is formed of a dielectric material, and is configured to allow conduction of charges between the first source/drain region and the conductive fill.

17. The semiconductor device of claim 16 , wherein the passivated layer is spaced apart from a gate spacer alongside the gate electrode.

18. The semiconductor device of claim 16 , wherein the passivated layer extends between the conductive fill and the ILD.

19. The semiconductor device of claim 18 , wherein the passivated layer is free from metal.

20. The semiconductor device of claim 16 , wherein the passivated layer has a thickness between 0.5 nm and 2 nm.