Methods, apparatus and system for a passthrough-based architecture
At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.
1. A method for forming a finFET device, comprising:
forming a first gate structure and a second gate structure on a semiconductor wafer;
forming a first active area on one end of said first and second gate structures;
forming a second active area on the other end of said first and second gate structures; and
forming a trench silicide (TS) structure self-aligned to said first and second gate structures, wherein said TS structure being configured to operatively couple said first active area to said second active area.
2. The method of claim 1 , further comprising forming a first CB structure above at least one of said gate structures, wherein said first CB structure is formed offset relative to said gate structure in a manner such that said first CB structure does not contact the TS structure.
3. The method of claim 2 , wherein forming said first CB structure comprises forming an elongated CB structure configured to provide increased contact area with said gate structure.
4. The method of claim 2 , wherein forming said first CB structure comprises forming said CB as a self-aligned via through an M0 metal formation.
5. The method of claim 1 , wherein forming said self-aligned TS structure comprises forming a self-aligned, borderless TS structure.
6. The method of claim 1 , wherein forming said self-aligned TS structure comprises:
using a first TS cut mask above said first active region to define a top border of said first active region;
using a second TS cut mask and a third TS cut mask for:
defining a bottom border of TS over said first active region;
defining a top border of TS over said second active region; and
defining the gates structures within which the TS structures is defined; and
using a fourth TS cut mask below said second active region to define a bottom border of TS over said second active region.
7. The method of claim 6 , further comprising forming a CA structure between said second and third TS cut masks, wherein said CA structure is formed to make contact with said TS structure and said first active area.
8. The method of claim 7 , wherein said CA structures is further defined by an M1 cut mask.
9. The method of claim 1 , wherein forming said first active area comprises forming a PMOS region and wherein forming said second active area comprises forming an NMOS region.
10. The method of claim 1 , wherein forming said first and second gate structures comprises forming a contacted poly pitch (CPP) that is 63 nm in width on a 10 nm architecture.