Data register copying for non-volatile storage array operations

1. An apparatus comprising:

an array of non-volatile storage cells;

a controller configured to indicate whether a burst mode is set for the array;

a set of write buffer data registers configured to store target data for a program operation for the array, wherein the write buffer data registers communicate the target data to corresponding columns of the array; and

a set of shadow data registers configured to receive the target data from peripheral circuitry for the array, wherein a portion of the target data received by a shadow data register is duplicated at a corresponding write buffer data register while the shadow data register receives the portion of the target data in response to the controller indicating that the burst mode is set for the array.

2. The apparatus of claim 1 , wherein the set of shadow data registers is configured to copy multiple portions of the target data to corresponding write buffer data registers after the shadow data registers receive the multiple portions of the target data, in response to the controller indicating that the burst mode is not set for the array.

3. The apparatus of claim 1 , wherein a program operation writes a first portion of the target data from a first write buffer data register to the array while a subsequent shadow data register receives a subsequent portion of the target data.

4. The apparatus of claim 1 , wherein data duplicated at the write buffer data registers is maintained in the shadow data registers, such that the shadow data registers are configured as a cache for the write buffer data registers.

5. The apparatus of claim 1 , wherein multiple write buffer data registers correspond to a column of the array, and wherein portions of the target data for the multiple write buffer data registers are received by one shadow data register for the column.

6. The apparatus of claim 1 , wherein:

the set of write buffer data registers is further configured to receive read data from the array for a read operation; and

the set of shadow data registers is further configured to output the read data to the peripheral circuitry for the array, wherein a portion of the read data received by a write buffer data register is duplicated at a corresponding shadow data register while the write buffer data register receives the same portion of the read data.

7. The apparatus of claim 1 , wherein the inputs for the set of shadow data registers are coupled to one input line from the peripheral circuitry, and the shadow data registers are configured to be activated one at a time to communicate via the input line.

8. The apparatus of claim 1 , wherein the outputs for the set of write buffer data registers are coupled to one output line to the array, and the write buffer data registers are configured to be activated one at a time to communicate via the output line.

9. A method comprising:

receiving target data, using a shadow data latch, for a program operation that writes the target data to an array of non-volatile memory cells;

determining whether a burst mode is set for the array;

copying the target data to a write buffer data latch before additional target data for the program operation using the array is received by an adjacent shadow data latch, in response to determining that the burst mode is set for the array; and

writing the target data from the write buffer data latch to the array.

10. The method of claim 9 , further comprising copying multiple bits of target data from a plurality of shadow data latches to a corresponding plurality of write buffer data latches after the plurality of shadow data latches receives the multiple bits of target data, in response to determining that the burst mode is not set for the array.

11. The method of claim 9 , further comprising receiving the additional target data using the adjacent shadow data latch while writing the target data from the write buffer data latch to the array.

12. The method of claim 9 , further comprising maintaining the target data in the shadow data latch such that the shadow data latch is configured as a cache for the write buffer data latch.

13. The method of claim 9 , further comprising receiving further target data for one column of the array, using the shadow data latch, and copying the further target data to one or more additional write buffer data latches for the column.

14. The method of claim 9 , further comprising:

reading data from the array to the write buffer data latch;

copying the read data to the shadow data latch before additional read data is received by an adjacent write buffer data latch; and

outputting the read data from the shadow data latch to peripheral circuitry for the array.

15. The method of claim 9 , wherein receiving the target data comprises activating the shadow data latch to receive the target data over an input line shared by a set of shadow data latches.

16. The method of claim 9 , wherein writing the target data comprises activating the write buffer data latch to write the target data over an output line shared by a set of write buffer data latches.

17. An apparatus comprising:

means for receiving target data, using a set of shadow data registers, for a program operation that writes the target data to an array of non-volatile storage cells;

means for determining whether a burst mode is set for the array;

means for copying portions of the target data to a set of write buffer data registers, such that a portion of the target data received by a shadow data register is copied to a corresponding write buffer data register before a subsequent portion of the target data is received by an adjacent shadow data register, in response to determining that the burst mode is set for the array; and

means for writing the target data from the set of write buffer data registers to the array.