IP Library Granted Patent US 11,181,688
Granted Patent B2
US 11,181,688 · App. 15/073,957 · Granted Nov 23, 2021

Integration of an unprocessed, direct-bandgap chip into a silicon photonic device

Inventors: Stephen B. Krasulick (Albuquerque, NM); John Dallesasse (Geneva, IL); Amit Mizrahi (San Francisco, CA); Timothy Creazzo (Albuquerque, NM); Elton Marchena (Albuquerque, NM); John Y. Spann (Albuquerque, NM)
Assignee: Skorpios Technologies, Inc.
G02B6/12004H01S5/02326G02B2006/12176H01L2224/32225H01S5/005H01S5/14
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Quick Facts
Patent No.
US 11,181,688
App. No.
15/073,957
Granted
Nov 23, 2021
Kind
B2
Abstract

A composite device for splitting photonic functionality across two or more materials comprises a platform, a chip, and a bond securing the chip to the platform. The platform comprises a base layer and a device layer. The device layer comprises silicon and has an opening exposing a portion of the base layer. The chip, a material, comprises an active region (e.g., gain medium for a laser). The chip is bonded to the portion of the base layer exposed by the opening such that the active region of the chip is aligned with the device layer of the platform. A coating hermetically seals the chip in the platform.

Claims (70)

1. A composite device for splitting photonic functions across two or more materials, the composite device comprising:

a platform, the platform comprising:

a base layer, wherein:

the base layer comprises a plurality of walls;

a pedestal is defined in the base layer;

the pedestal and the base layer comprise a common material;

the pedestal defines a surface that is flat and that extends continuously across a center of the pedestal; and

a wall of the plurality of walls of the base layer extends from the surface of the pedestal to an insulating layer;

a device layer, wherein:

the device layer comprises a first material;

the first material is a semiconductor;

the device layer comprises a plurality of walls forming an opening in the device layer;

the plurality of walls of the device layer are coplanar with the plurality of walls of the base layer; and

the insulating layer, wherein the insulating layer is between the base layer and the device layer; and

an upper layer disposed on top of the device layer, such that the device layer is between the insulating layer and the upper layer, wherein an opening is formed in the upper layer by walls in the upper layer that are coplanar with the plurality of walls of the device layer;

a chip, wherein:

the chip comprises an active region;

the active region comprises a second material, different from the first material;

the chip defines a surface that is flat;

the surface of the chip and the surface of the pedestal are in direct contact with each other; and

the chip does not extend above a top surface of the upper layer of the platform;

a bond securing the chip to the platform, wherein:

the bond is separate from the pedestal;

the chip is secured to the base layer of the platform in the opening of the device layer; and

the device layer of the platform is optically aligned with the active region of the chip using the pedestal; and

a coating, wherein the coating hermetically seals the chip in the platform.

2. The composite device as recited in claim 1 , wherein:

the first material is silicon; and

the second material is a direct bandgap material.

3. The composite device as recited in claim 2 , wherein the direct bandgap material comprises III-V material.

4. The composite device as recited in claim 2 , wherein:

the first material is a crystalline semiconductor material;

the device layer of the platform comprises gratings;

the gratings are formed of the first material; and

the gratings are used as mirrors to form a laser cavity, with the chip being configured as a gain medium of the laser cavity.

5. The composite device as recited in claim 4 , wherein the gratings are binary superimposed (BSG) gratings.

6. The composite device as recited in claim 1 , wherein:

a gap separates the chip and a wall of the plurality of walls forming the opening; and

amorphous silicon and/or poly silicon at least partially fills the gap separating the chip and the wall of the plurality of walls.

7. The composite device as recited in claim 1 , wherein:

a gap separates the chip and a wall of the plurality of walls forming the opening;

two or more materials at least partially fill the gap;

the two or more materials have different indexes of refraction; and

the two or more materials contact each other.

8. The composite device as recited in claim 7 , wherein at least one of the two or more materials is silicon dioxide.

9. The composite device as recited in claim 1 , wherein:

the surface of the chip is a first surface;

the first surface of the chip is secured to the bond;

a contact metal is on a second surface of the chip; and

the first surface of the chip is opposite the second surface of the chip.

10. The composite device as recited in claim 1 , wherein:

the device layer of the platform comprises a ridge waveguide;

the chip comprises a ridge waveguide;

the ridge waveguide of the chip is aligned with the ridge waveguide of the platform; and

a ridge portion of the ridge waveguide of the chip and a ridge portion of the ridge waveguide of the platform extend along a direction of light propagation.

11. The composite device as recited in claim 10 , wherein the pedestal is directly under an optical path defined by the ridge portion of the ridge waveguide of the chip, at an edge of the chip.

12. The composite device as recited in claim 1 , wherein the bond is a metal bond.

13. The composite device as recited in claim 12 , wherein the bond comprises Indium and Palladium.

14. The composite device as recited in claim 1 , wherein:

the platform comprises a silicon-on-insulator (SOI) wafer having a handle portion and a buried-oxide (BOX) layer;

the base layer is the handle portion of the SOI wafer; and

the insulating layer is the BOX layer of the SOI wafer.

15. The composite device as recited in claim 1 , wherein at least one additional pedestal is defined in the base layer of the platform, such that the chip rests on the pedestal and the at least one additional pedestal to align the active region of the chip with the device layer of the platform.

16. The composite device as recited in claim 1 , wherein the coating comprises silicon dioxide.

17. The composite device as recited in claim 1 , wherein the device layer of the platform comprises an optical waveguide.

18. The composite device as recited in claim 1 , wherein the bond securing the chip to the platform uses under-bump metallization.

19. The composite device as recited in claim 1 , wherein a height of the wall extending from the surface of the pedestal to the insulating layer is equal to or greater than 10 nanometers and equal to or less than 150 nanometers.

20. The composite device as recited in claim 1 , wherein:

the chip comprises an etch stop; and

the active region is between the etch stop and the surface of the chip that is in contact with the pedestal.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Nov 22, 2017
From: PACIFIC WESTERN BANK
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 044751/0469 →
SECURITY INTEREST Recorded Oct 23, 2017
From: SKORPIOS TECHNOLOGIES, INC.
To: PACIFIC WESTERN BANK
Reel/Frame 043926/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2016
From: KRASULICK, STEPHEN B.; DALLESASSE, JOHN; MIZRAHI, AMIT; CREAZZO, TIMOTHY; MARCHENA, ELTON; SPANN, JOHN Y.
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 038937/0001 →
Continuity (12)
Continuation In Part 14509914 · Oct 8, 2014
Continuation In Part 14488041 · Sep 16, 2014
Continuation In Part 14262529 · Apr 25, 2014
Continuation In Part 13605633 · Sep 6, 2012
Continuation 13040181 · Mar 3, 2011
Continuation In Part 12903025 · Oct 12, 2010
Provisional Application 62028611 · Jul 24, 2014
Provisional Application 61888863 · Oct 9, 2013
Provisional Application 61815938 · Apr 25, 2013
Provisional Application 61532050 · Sep 7, 2011
Provisional Application 61251143 · Oct 13, 2009
Related Publication 20160274319A1 · Sep 22, 2016
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