IP Library › Granted Patent US 10,510,625
Granted Patent B2
US 10,510,625 · App. 15/074,808 · Granted Dec 17, 2019

Systems and methods for controlling plasma instability in semiconductor fabrication

Inventors: Yukinori Sakiyama (West Linn, OR); Edward Augustyniak (Tualatin, OR); Douglas Keil (West Linn, OR)
Assignee: Lam Research Corporation
H01L22/20C23C16/4585C23C16/4586C23C16/45565C23C16/50C23C16/509C23C16/52H01J37/32082H01J37/32091H01J37/3299H01J37/32137H01J37/32715H01J37/32935H01L21/0228H01L21/02274H01L21/263H01L21/3065H01L21/67069H01L21/67201H01L21/683H01L22/12H01J2237/334H01L21/02164
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,510,625
App. No.
15/074,808
Granted
Dec 17, 2019
Kind
B2
Abstract

An apparatus for supporting a wafer during a plasma processing operation includes a pedestal configured to have bottom surface and a top surface and a column configured to support the pedestal at a central region of the bottom surface of the pedestal. An electrical insulating layer is disposed over the top surface of the pedestal. An electrically conductive layer is disposed over the top surface of the electrical insulating layer. At least three electrically conductive support structures are distributed on the electrically conductive layer. The at least three support structures are configured to interface with a bottom surface of a wafer to physically support the wafer and electrically connect to the wafer. An electrical connection extends from the electrically conductive layer to connect with a positive terminal of a direct current power supply at a location outside of the pedestal.

Claims (33)

1. An apparatus for supporting a wafer during a plasma processing operation, comprising:

a pedestal configured to have a bottom surface and a top surface;

a column configured to support the pedestal at a central region of the bottom surface of the pedestal;

an electrical insulating layer disposed over the top surface of the pedestal;

an electrically conductive layer disposed over a top surface of the electrical insulating layer;

at least three support structures distributed on a top surface of the electrically conductive layer, each of the at least three support structures formed of electrically conductive material and secured in electrical contact with the electrically conductive layer, the at least three support structures configured to interface with a bottom surface of a wafer to physically support the wafer and electrically connect to the wafer; and

an electrical connection extending from the electrically conductive layer to a location outside of the pedestal, wherein the electrical connection is electrically connected to a positive terminal of direct current power supply so that the at least three support structures are electrically connected to the positive terminal of the direct current power supply.

2. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein the column is configured to rotate, the column fixed to the pedestal such that rotation of the column causes corresponding rotation of the pedestal.

3. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein the electrical insulating layer has a vertical thickness as measured in a direction perpendicular to the top surface of the pedestal at least large enough to prevent flow of electrical current from the electrically conductive layer to the pedestal.

4. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 3 , wherein the electrical insulating layer has a vertical thickness as measured in a direction perpendicular to the top surface of the pedestal within a range extending up to about 1000 micrometers, or within a range extending up to about 100 micrometers, or within a range extending from about 10 micrometers to about 50 micrometers, or of about 30 micrometers.

5. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein the electrically conductive layer has a vertical thickness as measured in a direction perpendicular to the top surface of the pedestal within a range extending up to about 1 millimeter, or within a range extending up to about 7 millimeters, or within a range extending up to about 13 millimeters.

6. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein the electrically conductive layer is formed as either a plate, or a laminated film, or a sprayed coating.

7. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein the at least three support structures are distributed in a substantially uniform manner across the electrically conductive layer.

8. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein the at least three support structures are distributed in a non-uniform manner across the electrically conductive layer.

9. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 8 , wherein a larger number of the at least three support structures are positioned near a peripheral region of the electrically conductive layer as compared to near a central region of the electrically conductive layer.

10. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein both the at least three support structures and the electrically conductive layer are formed of a same material.

11. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein the electrically conductive layer is formed of a material different than a material of which the at least three support structures are formed.

12. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein both the at least three support structures and the electrically conductive layer are formed as a single integral structure.

13. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein the at least three support structures are attached to the electrically conductive layer.

14. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein each of the at least three support structures is configured to have a rounded top surface for interfacing with the bottom surface of the wafer.

15. The apparatus for supporting the wafer during the plasma processing operation as recited in claim 1 , wherein the electrical insulating layer is formed integrally with the pedestal.

16. A system for plasma processing of a wafer, comprising:

a direct current power supply having a positive terminal and a negative terminal;

a low pass filter circuit having an input connection and an output connection, the input connection of the low pass filter circuit electrically connected to the positive terminal of the direct current power supply;

a wafer support apparatus including a pedestal configured to have a bottom surface and a top surface, the wafer support apparatus including an electrical insulating layer disposed over the top surface of the pedestal, the wafer support apparatus including an electrically conductive layer disposed over a top surface of the electrical insulating layer, the electrically

conductive layer including at least three support structures distributed on a top surface of the electrically conductive layer to physically contact and support a bottom surface of a wafer, each of the at least three support structures formed of electrically conductive material, each of the at least three support structures electrically connected to the output connection of the low pass filter circuit;

an electrode positioned above the wafer support apparatus, a plasma generation region located between the electrode and the wafer support apparatus;

a radiofrequency power supply connected to deliver radiofrequency power to the electrode; and

at least one electrically conductive structure exposed to the plasma generation region and electrically connected to the negative terminal of the direct current power supply.

17. The system for plasma processing of the wafer as recited in claim 16 , wherein the at least one electrically conductive structure exposed to the plasma generation region is the electrode.

18. The system for plasma processing of the wafer as recited in claim 16 , wherein the at least one electrically conductive structure exposed to the plasma generation region is a wall of a chamber in which the electrode and the wafer support apparatus are disposed.

19. The system for plasma processing of the wafer as recited in claim 16 , wherein the electrically conductive layer is electrically connected to the output connection of the low pass filter circuit.

20. The system for plasma processing of the wafer as recited in claim 19 , wherein the wafer support apparatus includes a column configured to support the pedestal at a central region of the bottom surface of the pedestal, and wherein the column is configured to rotate, the column fixed to the pedestal such that rotation of the column causes corresponding rotation of the pedestal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2016
From: SAKIYAMA, YUKINORI; AUGUSTYNIAK, EDWARD; KEIL, DOUGLAS
To: LAM RESEARCH CORPORATION
Reel/Frame 038036/0515 →
Continuity (2)
Provisional Application 62256682 · Nov 17, 2015
Related Publication 20170140968A1 · May 18, 2017
Cited By (1)
US 12,327,748