Package substrate and method of manufacturing the same
Package substrate and a method of manufacturing the same is disclosed. The package substrate includes an insulating layer having first circuit patterns embedded in a first surface of the insulating layer, and a protruded circuit pattern formed above at least one of the embedded first circuit patterns, wherein a width of the protruded circuit pattern is greater than a width of each of the embedded first circuit patterns. Accordingly, a flip chip and a wire bonding chip may be installed at the same time owing to an embedded structure of circuit pattern and a protruded structure of circuit pattern realized together on a surface where an electronic component is to be installed. Moreover, a fine circuit pattern may be formed, and a surface treatment layer may be selectively formed at desired portions without forming an additional seed layer for electroplating, thereby possibly simplifying manufacturing processes and saving manufacturing costs.
1. A package substrate, comprising:
an insulating layer having first circuit patterns embedded in a first surface of the insulating layer;
a protruded circuit pattern formed above at least one of the embedded first circuit patterns; and
a solder resist layer in a pattern that covers a portion of the first circuit patterns and a portion of the first surface of the insulating layer, and exposes a portion of the first circuit patterns and a portion of the first surface of the insulating layer,
wherein a width of the protruded circuit pattern is greater than a width of the at least one of the embedded first circuit patterns,
wherein a depth of the at least one of the embedded first circuit patterns is less than a depth of the insulating layer, and
wherein lateral surfaces of the protruded circuit pattern are separated from the solder resist layer.
2. The package substrate of claim 1 , further comprising a surface treatment layer formed above the protruded circuit pattern.
3. The package substrate of claim 2 , wherein a surface of the surface treatment layer comprises a first layer electroplated on a second layer.
4. The package substrate of claim 1 , wherein a surface of the each of the embedded first circuit patterns is formed on a same plane as the first surface of the insulating layer.
5. The package substrate of claim 1 , further comprising a second circuit patter formed on a second surface of the insulating layer.
6. The package substrate of claim 5 , further comprising a via to electrically connect the first circuit patterns with the second circuit pattern.
7. The package substrate of claim 6 , wherein the solder resist layer covers a portion of the first circuit patterns, a portion of the first surface of the insulating layer, a portion of the second circuit patter, and a portion of the second surface of the insulating layer.
8. The package substrate of claim 5 , wherein the second surface of the insulating layer is disposed parallel and opposite to the first surface of the insulating layer.
9. The package substrate of claim 1 , wherein a surface of the protruded circuit pattern is disposed parallel to and above the first surface.
10. The package substrate of claim 1 , wherein a width of the protruded circuit patter is greater than twice as large as a width of the at least one of the embedded first circuit patterns.