IP Library Granted Patent US 9,652,386
Granted Patent B2
US 9,652,386 · App. 15/094,844 · Granted May 16, 2017

Management of memory array with magnetic random access memory (MRAM)

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Quick Facts
Patent No.
US 9,652,386
App. No.
15/094,844
Granted
May 16, 2017
Kind
B2
Abstract

An embodiment of the present invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array and NAND array and a hybrid user area made of a combination of MRAM array and NAND array. The mass storage device further includes a controller with a host interface and a flash interface coupled to the MRAM and NAND flash memory devices through the flash interface.

Claims (20)

1. A mass storage device comprising:

one or more MRAM devices including a first interface circuit;

one or more NAND flash memory devices including a second interface circuit;

a hybrid reserved area spanning at least a portion of the one or more MRAM devices; and

a controller coupled to the one or more MRAM devices through the first interface circuit and to the one or more NAND flash memory devices through the second interface circuit.

2. The mass storage device of claim 1 , wherein the first interface circuit is a NAND interface circuit.

3. The mass storage device of claim 1 , wherein the second interface circuit is a NAND interface circuit.

4. The mass storage device of claim 1 , wherein the hybrid reserved area further spans at least a portion of the one or more NAND flash memory devices.

5. The mass storage device of claim 4 , wherein the controller uses the hybrid reserved area to store private data comprising tables, boot code, system data, Meta data or any combination thereof.

6. The mass storage device of claim 1 , wherein the controller uses the hybrid reserved area to store private data comprising tables, boot code, system data, Meta data or any combination thereof.

7. The mass storage device of claim 1 , wherein the controller further uses the hybrid reserved area to store tables.

8. The mass storage device of claim 7 , wherein the hybrid reserved area further spans at least a portion of the one or more NAND flash memory devices and further wherein the controller is operable to maintain at least a portion of the tables in the at least a portion of the one or more NAND flash devices.

9. The mass storage device of claim 8 , wherein periodically at least a portion of the tables is moved from the at least a portion of the one or more MRAM devices to the at least a portion of the one or more NAND flash memory devices.

10. The mass storage device of claim 1 , wherein the controller is responsive to host data and operable to cache the host data in the at least a portion of the one or more MRAM devices.

11. The mass storage device of claim 10 , further including a user area that spans at least a portion of the one or more NAND flash memory devices, wherein the controller is operable to move the cached host data to the user area.

12. The mass storage device of claim 11 , wherein the hybrid reserved area further spans at least another portion of the one or more NAND flash memory devices.

13. The mass storage device of claim 11 , wherein upon unavailability of storage space in the NAND flash memory devices, the controller is operable to perform “garbage collection” to make space available in the NAND flash memory devices prior to moving the cached host data from the MRAM devices to the NAND flash memory devices.

14. The mass storage device of claim 11 , wherein upon the cached host data being re-written prior to being moved to the user area, the controller is operable to overwrite the cached host data.

15. The mass storage device of claim 11 , wherein upon the cached host data being read prior to being moved to the user area, the controller is operable to read the cached host data.

16. The mass storage device of claim 11 , wherein the controller is operable to cache adequate host data to perform a NAND flash full page program operation on the user area.

Assignments (6)
SECURITY INTEREST Recorded Mar 18, 2022
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 059436/0203 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057213/0050 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057217/0674 →
SECURITY INTEREST Recorded Jul 8, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: SILICON VALLEY BANK
Reel/Frame 053156/0223 →
SECURITY INTEREST Recorded Feb 13, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 051930/0396 →
SECURITY INTEREST Recorded Apr 18, 2017
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 042273/0813 →