IP Library Granted Patent US 9,929,234
Granted Patent B2
US 9,929,234 · App. 15/144,842 · Granted Mar 27, 2018

Semiconductor device having a cap layer with V-shape

Inventors: Chih-Kai Hsu (Tainan, TW); Ssu-I Fu (Kaohsiung, TW); Yu-Hsiang Hung (Tainan, TW); Wei-Chi Cheng (Kaohsiung, TW); Jyh-Shyang Jenq (Pingtung County, TW); Tsung-Mu Yang (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/0653H01L21/76895H01L23/535H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 9,929,234
App. No.
15/144,842
Granted
Mar 27, 2018
Kind
B2
Abstract

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

Claims (12)

1. A semiconductor device, comprising:

a substrate;

a gate structure on the substrate;

an epitaxial layer structure in the substrate adjacent to two sides of the gate structure; and

a cap layer on the epitaxial layer, wherein the cap layer comprises a first V-shape and a first valley point of the first V-shape is lower than a top surface of the substrate.

2. The semiconductor device of claim 1 , further comprising a buffer layer between the epitaxial layer and the substrate.

3. The semiconductor device of claim 2 , wherein the buffer layer comprises silicon phosphide (SiP).

4. The semiconductor device of claim 1 , wherein the epitaxial layer and the cap layer comprises SiP.

5. The semiconductor device of claim 4 , wherein a concentration of the phosphorus in the cap layer is lower than a concentration of the phosphorus in the epitaxial layer.

6. The semiconductor device of claim 1 , wherein a top surface of the epitaxial layer comprises a second V-shape and a second valley point of the second V-shape is lower than a top surface of the substrate.

7. The semiconductor device of claim 1 , further comprising a contact plug contacting the cap layer.

8. The semiconductor device of claim 1 , wherein a thickness of the cap layer is between 10-100 Angstroms.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: UNITED MICROELECTRONICS CORP.
To: STELLAR SEMICONDUCTOR JAPAN GK
Reel/Frame 071913/0125 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2016
From: HSU, CHIH-KAI; FU, SSU-I; HUNG, YU-HSIANG; CHENG, WEI-CHI; JENQ, JYH-SHYANG; YANG, TSUNG-MU
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 038441/0675 →
Priority Claims (1)
CN 2016 1 0209916 · Apr 6, 2016 · national
Continuity (1)
Related Publication 20170294508A1 · Oct 12, 2017