IP Library Granted Patent US 9,530,479
Granted Patent B2
US 9,530,479 · App. 15/147,084 · Granted Dec 27, 2016

Method and apparatus for increasing the reliability of an access transistor coupled to a magnetic tunnel junction (MTJ)

Inventor: Ebrahim Abedifard (San Jose, CA)
Assignee: Avalanche Technology, Inc.
G11C11/1675G11C11/161
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Quick Facts
Patent No.
US 9,530,479
App. No.
15/147,084
Granted
Dec 27, 2016
Kind
B2
Abstract

A method is disclosed for writing a magnetic tunnel junction (MTJ) of a magnetic memory array by switching a magnetic orientation associated with the MTJ from anti-parallel to parallel magnetic orientation. One end of the MTJ is coupled to a bit line while the opposite end of the MTJ is coupled to one end of an access transistor. The method includes the steps of applying a gate voltage that is approximately a sum of a first voltage and a second voltage to a gate of the access transistor with the second voltage being less than the first voltage; raising the bit line to the first voltage; and applying the second voltage to the opposite end of the access transistor to program the MTJ while maintaining a voltage difference between the gate and the one end of the access transistor to be less than or equal to the first voltage.

Claims (19)

1. A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array by switching a magnetic orientation associated with the MTJ from an anti-parallel to a parallel magnetic orientation, one end of the MTJ being coupled to a bit line and the opposite end of the MTJ being coupled to one of a source and a drain of an access transistor, the method comprising the steps of:

applying a gate voltage that is approximately a sum of a first voltage and a second voltage to a gate of the access transistor, the second voltage being less than the first voltage;

raising the bit line to the first voltage; and

applying the second voltage to the other one of the source and the drain of the access transistor to program the MTJ while maintaining a voltage difference between the gate and the one of the source and the drain of the access transistor to be less than or equal to the first voltage.

2. The method of claim 1 , wherein the drain of the access transistor is coupled to the MTJ.

3. The method of claim 1 , wherein the first voltage is approximately Vcc and the second voltage is approximately Vx.

4. The method of claim 1 , wherein the gate of the access transistor is coupled to a word line.

5. The method of claim 1 , wherein the other one of the source and the drain of the access transistor is coupled to a source line.

6. The method of claim 1 , wherein a current flows from a free layer to a fixed layer in the MTJ to switch the magnetization orientation thereof from the anti-parallel to the parallel magnetic orientation.

7. A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array by switching a magnetic orientation associated with the MTJ from a parallel to an anti-parallel magnetic orientation, one end of the MTJ being coupled to a bit line and the opposite end of the MTJ being coupled to one of a source and a drain of an access transistor, the method comprising the steps of:

applying a gate voltage that is approximately a sum of a first voltage and a second voltage to a gate of the access transistor, the second voltage being less than the first voltage;

applying the first voltage to the other one of the source and the drain of the access transistor; and

applying a third voltage to the bit line to program the MTJ while maintaining a voltage difference between the gate and the other one of the source and the drain of the access transistor to be less than or equal to the first voltage.

8. The method of claim 7 , wherein the source of the access transistor is coupled to the MTJ.

9. The method of claim 7 , wherein the first voltage is approximately Vcc and the second voltage is approximately Vx.

10. The method of claim 7 , wherein the third voltage is approximately 0 volt.

11. The method of claim 7 , wherein the gate of the access transistor is coupled to a word line.

12. The method of claim 7 , wherein the other one of the source and the drain of the access transistor is coupled to a source line.

13. The method of claim 7 , wherein a current flows from a fixed layer to a free layer in the MTJ to switch the magnetization orientation thereof from the parallel to the anti-parallel magnetic orientation.

Assignments (7)
SECURITY INTEREST Recorded Mar 18, 2022
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 059436/0203 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057213/0050 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057217/0674 →
SECURITY INTEREST Recorded Jul 8, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: SILICON VALLEY BANK
Reel/Frame 053156/0223 →
SECURITY INTEREST Recorded Feb 13, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 051930/0396 →
SECURITY INTEREST Recorded Apr 18, 2017
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 042273/0813 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2016
From: ABEDIFARD, EBRAHIM
To: AVALANCHE TECHNOLOGY, INC.
Reel/Frame 038612/0556 →
Continuity (7)
Continuation 14552447 · Nov 24, 2014
Continuation 13625586 · Sep 24, 2012
Continuation 12860793 · Aug 20, 2010
Continuation In Part 12826546 · Jun 29, 2010
Continuation In Part 12756081 · Apr 7, 2010
Provisional Application 61167859 · Apr 8, 2009
Related Publication 20160254042A1 · Sep 1, 2016