Sense amplifier local feedback to control bit line voltage
Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.
1. An apparatus, comprising:
a first bit line biasing circuit including a first transistor, a source of the first transistor connected to a first bit line, the first bit line connected to a first memory cell, the first bit line biasing circuit configured to set a gate of the first transistor to a first voltage such that the first bit line is biased towards a particular voltage during a first time period;
a third transistor, a gate of the third transistor connected to the source of the first transistor, a drain of the third transistor connected to the gate of the first transistor;
a second bit line biasing circuit including a second transistor, a source of the second transistor connected to a second bit line, the second bit line connected to a second memory cell, the second memory cell and the first memory cell are connected to a word line, the second bit line biasing circuit configured to set a gate of the second transistor to a second voltage different from the first voltage such that the second bit line is biased towards the particular voltage during the first time period; and
a fourth transistor, a gate of the fourth transistor connected to the source of the second transistor, a drain of the fourth transistor connected to the gate of the second transistor.
2. The apparatus of claim 1 , wherein:
the first bit line is biased at the particular voltage during the first time period; and
the second bit line is biased at the particular voltage during the first time period.
3. The apparatus of claim 1 , wherein:
the particular voltage comprises a read voltage during the first time period; and
the first voltage is greater than the second voltage during the first time period.
4. The apparatus of claim 1 , wherein:
the first bit line biasing circuit configured to determine the first voltage based on feedback from the first bit line; and
the second bit line biasing circuit configured to determine the second voltage based on feedback from the second bit line.
5. The apparatus of claim 1 , further comprising:
a word line driver configured to set the word line to ground during the first time period.
6. The apparatus of claim 1 , wherein:
the first transistor comprises a first NMOS transistor; and
the second transistor comprises a second NMOS transistor.
7. The apparatus of claim 1 , wherein:
the first memory cell and the second memory cell are part of a cross-point memory array.
8. The apparatus of claim 1 , wherein:
the first memory cell comprises a two-terminal memory cell.
9. The apparatus of claim 1 , wherein:
the first memory cell comprises a resistance-switching material.
10. The apparatus of claim 9 , wherein:
the resistance-switching material comprises a metal oxide.
11. A system, comprising:
means for electrically connecting a source of a first transistor to a first bit line, the first bit line connected to a first memory cell;
means for electrically connecting a source of a second transistor to a second bit line, the second bit line connected to a second memory cell, the second memory cell and the first memory cell are connected to a word line;
means for setting the gate of the first transistor to a first voltage such that the first bit line is biased at a particular voltage during a first time period;
means for setting the gate of the second transistor to a second voltage different from the first voltage such that the second bit line is biased at the particular voltage during the first time period;
means for sensing a first current through the first memory cell during the first time period while the gate of the first transistor is set to the first voltage; and
means for sensing a second current through the second memory cell during the first time period while the gate of the second transistor is set to the second voltage.
12. The system of claim 11 , wherein:
the first memory cell and the second memory cell are part of a cross-point memory array.
13. The system of claim 11 , wherein:
the first memory cell comprises a two-terminal memory cell.
14. An apparatus, comprising:
a first biasing circuit including a first transistor, a source of the first transistor connected to a first bit line, the first bit line connected to a first memory cell, the first biasing circuit configured to bias a gate of the first transistor to a first voltage such that the first bit line is biased at a particular voltage during a first time period, the first voltage is generated based on feedback from the first bit line;
a third transistor, a gate of the third transistor connected to the source of the first transistor, a drain of the third transistor connected to the gate of the first transistor;
a second biasing circuit including a second transistor, a source of the second transistor connected to a second bit line, the second bit line connected to a second memory cell, the second memory cell and the first memory cell are connected to a word line, the second biasing circuit configured to bias a gate of the second transistor to a second voltage different from the first voltage such that the second bit line is biased at the particular voltage during the first time period, the second voltage is generated based on feedback from the second bit line; and
a fourth transistor, a gate of the fourth transistor connected to the source of the second transistor, a drain of the fourth transistor connected to the gate of the second transistor.
15. The apparatus of claim 14 , wherein:
the particular voltage comprises a read voltage during the first time period; and
the first voltage is greater than the second voltage during the first time period.
16. The apparatus of claim 14 , wherein:
the first memory cell and the second memory cell are part of a cross-point memory array.
17. The apparatus of claim 14 , wherein:
the first memory cell comprises a two-terminal memory cell.