IP Library Granted Patent US 10,224,367
Granted Patent B2
US 10,224,367 · App. 15/157,607 · Granted Mar 5, 2019

Selector device incorporating conductive clusters for memory applications

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Quick Facts
Patent No.
US 10,224,367
App. No.
15/157,607
Granted
Mar 5, 2019
Kind
B2
Abstract

The present invention is directed to a memory device that includes an array of memory cells. Each of the memory cells includes a memory element connected to a two-terminal selector element. The two-terminal selector element includes a first electrode and a second electrode with a switching layer interposed therebetween. The switching layer includes a plurality of metal-rich clusters embedded in a nominally insulating matrix. One or more conductive paths are formed in the switching layer when an applied voltage to the memory cell exceeds a threshold level. Each of the memory cells may further include an intermediate electrode interposed between the memory element and the two-terminal selector element. The two-terminal selector element may further include a third electrode formed between the first electrode and the switching layer, and a fourth electrode formed between the second electrode and the switching layer.

Claims (24)

1. A memory device comprising an array of memory cells, each of said memory cells including a memory element connected to a two-terminal selector element, said two-terminal selector element comprising a first electrode and a second electrode with a switching layer interposed therebetween, said switching layer including a plurality of metal-rich clusters embedded in a matrix, wherein said switching layer has single resistance state in absence of an applied voltage thereto.

2. The memory device of claim 1 further comprising:

a plurality of first conductor lines extending along a first direction, each of said first conductor lines being coupled to a respective row of said memory cells at one ends; and

a plurality of second conductor lines extending along a second direction substantially perpendicular to said first direction, each of said second conductor lines being coupled to a respective row of said memory cells at the other ends.

3. The memory device of claim 1 , wherein said matrix is made of a chalcogenide.

4. The memory device of claim 1 , wherein said matrix is made of an oxide.

5. The memory device of claim 1 , wherein said matrix is made of an insulator.

6. The memory device of claim 1 , wherein said matrix is noncrystalline.

7. The memory device of claim 1 , wherein said plurality of metal-rich clusters are made of a material selected from the group consisting of silver, copper, zinc, titanium, titanium nitride, tantalum nitride, tungsten, and any combinations thereof.

8. The memory device of claim 1 , wherein said first and second electrodes are made of a same material.

9. The memory device of claim 1 , wherein each of said first and second electrodes is made of a material selected from the group consisting of platinum, iridium, ruthenium, gold, and any combinations thereof.

10. The memory device of claim 1 , wherein said plurality of metal-rich clusters and at least one of said first and second electrodes are made of a same material.

11. The memory device of claim 1 , wherein each of said memory cells further includes an intermediate electrode interposed between said memory element and said two-terminal selector element.

12. The memory device of claim 11 , wherein said intermediate electrode is made of a silicide or a nitride.

13. The memory device of claim 1 , wherein said memory element includes a magnetic free layer and a magnetic reference layer with an insulating tunnel junction layer interposed therebetween.

14. The memory device of claim 13 , wherein said magnetic free layer has a variable magnetization direction substantially perpendicular to a layer plane thereof, said magnetic reference layer has a fixed magnetization direction substantially perpendicular to a layer plane thereof.

15. The memory device of claim 1 , wherein said two-terminal selector element further comprises:

a third electrode formed between said first electrode and said switching layer; and

a fourth electrode formed between said second electrode and said switching layer.

16. The memory device of claim 15 , wherein said third and fourth electrodes are made of a same material.

17. The memory device of claim 15 , wherein said plurality of metal-rich clusters and at least one of said third and fourth electrodes are made of a same material.

18. The memory device of claim 15 , wherein said plurality of metal-rich clusters are made of a material selected from the group consisting of titanium nitride, tantalum nitride, tungsten, and any combinations thereof, each of said third and fourth electrodes is made of a material selected from the group consisting of silver, copper, zinc, titanium, and any combinations thereof.

19. The memory device of claim 15 , wherein each of said first and second electrodes is made of a material selected from the group consisting of platinum, iridium, ruthenium, and any combinations thereof, said plurality of metal-rich clusters and said third and fourth electrodes are made of a same material selected from the group consisting of silver, copper, zinc, titanium, and any combinations thereof.

20. A memory device comprising an array of memory cells, each of said memory cells including a memory element connected to a two-terminal selector element, said two-terminal selector element comprising a first electrode and a second electrode with a switching layer interposed therebetween, said switching layer including a plurality of metal-rich clusters embedded in a matrix, wherein each of said first and second electrodes is made of a material selected from the group consisting of iridium, ruthenium, and any combinations thereof.

Assignments (7)
SECURITY INTEREST Recorded Mar 18, 2022
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 059436/0203 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057213/0050 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057217/0674 →
SECURITY INTEREST Recorded Jul 8, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: SILICON VALLEY BANK
Reel/Frame 053156/0223 →
SECURITY INTEREST Recorded Feb 13, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 051930/0396 →
SECURITY INTEREST Recorded Apr 18, 2017
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 042273/0813 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2016
From: YANG, HONGXIN; SATOH, KIMIHIRO; WANG, XIAOBIN
To: AVALANCHE TECHNOLOGY, INC.
Reel/Frame 038632/0549 →