IP Library Granted Patent US 9,645,198
Granted Patent B2
US 9,645,198 · App. 15/159,171 · Granted May 9, 2017

Full/reduced pin JTAG interface shadow protocol detection, command, address circuits

Inventor: Lee D. Whetsel (Parker, TX)
Assignee: Texas Instruments Incorporated
G01R31/3177G01R31/2815G01R31/3025G01R31/31703G01R31/31727G01R31/318558G01R31/2851
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Quick Facts
Patent No.
US 9,645,198
App. No.
15/159,171
Granted
May 9, 2017
Kind
B2
Abstract

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices ( 504 ), only reduced pin JTAG devices ( 506 ), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface ( 502 ) between the substrate ( 408 ) and a JTAG controller ( 404 ). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Claims (10)

1. A shadow protocol circuit comprising:

(a) a shadow protocol detection circuit having a test data in input, a test clock input, a test mode select input, an enable output, a command output, a command control output, a match input, an address output, and an address control output;

(b) a command circuit having a command input connected to the command output, a command control input connected to the command control output, a full pin select output, and a reduced pin select output; and

(c) an address circuit including:

i. a shift register having an address input coupled to the address output, an address clock input coupled to the address control output, and a shifted address output;

ii. an update register having an input coupled to the shifted address output, an address update input, and an update output;

iii. a device address circuit having a device address output; and

iv. comparator circuitry having an input coupled to the device address output, an input coupled to the update output, and a match output coupled to the match input.

2. The shadow protocol circuit of claim 1 including a mode gate having one input connected to the test mode select input, and another input connected to the enable output.

3. The shadow protocol circuit of claim 1 including a tri-state gate having one input connected to a test data out lead, an output connected to a gated test data out lead, and a control input connected to the enable output.

Continuity (8)
Division 14815396 · Jul 31, 2015
Division 14456125 · Aug 11, 2014
Division 13488956 · Jun 5, 2012
Division 13078621 · Apr 1, 2011
Division 12883629 · Sep 16, 2010
Division 11874594 · Oct 18, 2007
Provisional Application 60829979 · Oct 18, 2006
Related Publication 20160259003A1 · Sep 8, 2016