FINFET circuit structures with vertically spaced transistors and fabrication methods
Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor. In another embodiment, the first transistor includes a fin structure extending from the substrate, and an upper portion of the fin structure includes the first channel region and a lower portion of the fin structure includes the isolation region.
1. A method comprising:
fabricating a circuit structure, the fabricating comprising:
providing a first transistor above a substrate, the providing comprising disposing a fin having a first channel region of the first transistor above the substrate above an isolation region, wherein the fin is entirely above a top surface of the isolation region;
providing a second transistor, the providing comprising providing a second channel region of the second transistor within, and surrounded by, the substrate, the second channel region being entirely lower than a bottom surface of the isolation region and laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by a thickness of the isolation region thereof; and
forming a first gate conformally over and in electrical contact with the fin of the first transistor and over the second channel region of the second transistor.
2. The method of claim 1 , further comprising forming a second gate over a third channel region of a third transistor, the third transistor comprising a second fin, adjacent the second transistor, having the third channel region of the third transistor above the substrate above a second isolation region, wherein the second fin is entirely above a top surface of the second isolation region.
3. The method of claim 2 , further comprising planarizing the first and second gates to facilitate formation of laterally coplanar metal layers above the circuit structure.
4. The method of claim 2 , wherein forming the first gate comprises depositing a first work function material over the first channel region of the first transistor and depositing a second work function material over the second channel region of the second transistor.
5. The method of claim 1 , wherein providing the first transistor comprises providing the first transistor as a p-type transistor and providing the second transistor comprises providing the second transistor as an n-type transistor.
6. The method of claim 1 , wherein fabricating the circuit structure comprises fabricating an inverter, wherein the first and second channel regions being vertically spaced apart facilitates inhibition of a leakage current of the inverter.
7. The of method claim 1 , wherein fabricating the circuit structure comprises fabricating a static random access memory, wherein the first and second channel regions being vertically spaced apart facilitates inhibition of a leakage current of the static random access memory.