Method of utilizing trench silicide in a gate cross-couple construct
A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.
1. A method comprising:
forming first and second active fins and first and second dummy fins on a substrate, the first and second dummy fins adjacent to each other and between the first and second active fins;
forming shallow trench insolation (STI) regions between and next to the first and second active fins and the first and second dummy fins;
forming first and second self-aligned gate structures in parallel across the first and second active fins and the first and second dummy fins;
forming first and second capping layers on the first and second self-aligned gate structures, respectively;
forming a gate cut region by cutting both the first and second self-aligned gate structures and the first and second capping layers between the first and second dummy fins;
forming a trench silicide (TS) layer between the first and second gate structures, the TS layer crossing the gate cut region; and
forming a first self-aligned contact connecting the first gate structure and the TS layer on a first side of the gate cut region and forming a second self-aligned contact connected to the second gate structure and the TS layer on a second side of the gate cut region, the TS and the first and second self-aligned contacts cross coupling the first and second gate structures.
2. The method according to claim 1 , comprising forming the TS layer over at least one STI region.
3. The method according to claim 1 , comprising forming the TS layer to approximately a same height as the height of the first and second self-aligned gate structures.
4. The method according to claim 3 , further comprising forming connected p-type metal-oxide-semiconductor (pMOS) and n-type MOS (nMOS) gate transistors with the first and second active fins, respectively, and the cross-coupled first and second self-aligned gate structures.
5. The method according to claim 1 , comprising forming the first and second self-aligned contacts in the first and second capping layers, down to the first and second gate structures, respectively.
6. The method according to claim 1 , comprising forming the first and second self-aligned contacts as rectangles perpendicular to the first and second gate structures, at angles to the first and second gate structures.
7. The method according to claim 1 , comprising forming the first and second self-aligned contacts in a “L” shape.
8. The method according to claim 1 , comprising forming the TS layer of tungsten (W).
9. The method according to claim 1 , further comprising forming a metal layer on top of the first and second self-aligned contacts.
10. A method comprising:
forming first and second active fins and first and second dummy fins, the first and second dummy fins adjacent to each other and between the first and second active fins;
forming shallow trench insolation (STI) regions between the first and second active fins and the first and second dummy fins;
forming first and second self-aligned gate structures across the first and second active fins and the first and second dummy fins;
forming first and second capping layers on the first and second self-aligned gate structures, respectively;
forming a gate cut region by cutting both the first and second self-aligned gate structures and the first and second capping layers between the first and second dummy fins;
forming a trench silicide (TS) layer between the first and second gate structures, the TS layer crossing the gate cut region; and
forming a first self-aligned contact connecting the first gate structure and the TS layer and forming a second self-aligned contact connected to the second gate structure and the TS layer, the TS layer and the first and second self-aligned contacts cross coupling the first and second gate structures.
11. The method according to claim 10 , comprising forming the TS layer over at least one STI region.
12. The method according to claim 10 , comprising forming the TS layer to approximately a same height as the height of the first and second self-aligned gate structures.
13. The method according to claim 12 , further comprising forming connected p-type metal-oxide-semiconductor (pMOS) and n-type MOS (nMOS) gate transistors with the first and second active fins, respectively, and the cross-coupled first and second self-aligned gate structures.
14. The method according to claim 10 , comprising forming the first and second self-aligned contacts in the first and second capping layers, down to the first and second gate structures, respectively.
15. The method according to claim 10 , comprising forming the first and second self-aligned contacts as rectangles perpendicular to the first and second gate structures, at angles to the first and second gate structures.
16. The method according to claim 10 , comprising forming the first and second self-aligned contacts in a “L” shape.
17. The method according to claim 10 , comprising forming the TS layer of tungsten (W).
18. The method according to claim 10 , further comprising forming a metal layer on top of the first and second self-aligned contacts.
19. A method comprising:
forming first and second active fins and first and second dummy fins on a substrate, the first and second dummy fins adjacent to each other and between the first and second active fins;
forming shallow trench insolation (STI) regions between and next to the first and second active fins and the first and second dummy fins;
forming first and second self-aligned gate structures in parallel across the first and second active fins and the first and second dummy fins;
forming first and second capping layers on the first and second self-aligned gate structures, respectively;
forming a gate cut region by cutting both the first and second self-aligned gate structures and the first and second capping layers between the first and second dummy fins;
forming a trench silicide (TS) layer formed of tungsten (W) between the first and second gate structures, the TS layer:
crossing the gate cut region,
formed over at least one STI region, and
formed to approximately the same height as a height of the first and second self-aligned gate structures;
forming a first self-aligned contact connecting the first gate structure and the TS layer on a first side of the gate cut region and forming a second self-aligned contact connected the second gate structure and the TS layer on a second side of the gate cut region, the TS and the first and second self-aligned contacts cross coupling the first and second gate structures; and
forming connected p-type metal-oxide-semiconductor (pMOS) and n-type MOS (nMOS) gate transistors with the first and second active fins, respectively, and the cross-coupled first and second self-aligned gate structures.
20. The method according to claim 19 , comprising forming the first and second self-aligned contacts as rectangles perpendicular to the first and second gate structures, at angles to the first and second gate structures, or in a “L” shape.