Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells
A six-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. Methods of increasing the operational speed in reading the contents of a selected memory cell in an array of such memory cells while lowering power consumption, and of avoiding an indeterminate memory cell state when a memory cell is “awakened” from Standby are described.
1. For an integrated circuit having an array of SRAM cells interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each SRAM cell having a pair of cross-coupled thyristors, each thyristor having first and second semiconductor regions intermediate an anode and a cathode, a first intermediate region of one thyristor connected to the second intermediate region of the other thyristor and a second intermediate region of the one thyristor connected to the first intermediate region of the other thyristor, each thyristor having an anode connected to a first supply voltage and a cathode connected to a second supply voltage, and a pair of bipolar select transistors, each bipolar select transistor having a collector region connected to one of a complementary bit line pair, and an emitter region connected to the first intermediate region of one of the thyristors, and having a base region connected to a word line, a method of reading an SRAM cell in the array comprising:
selecting at least one SRAM cell;
raising the first supply voltage from a standby mode voltage of the at least one selected SRAM cell; and
raising the voltage on the word line connected to the bipolar select transistors of the at least one selected SRAM cell with a delay after the step of raising the first supply voltage;
whereby a state of the at least one selected SRAM cell is read through a complementary bit line pair connected to the bipolar select transistors of the at least one selected SRAM cell.
2. The method of claim 1 wherein the delay is in the range of 10-60 picoseconds.
3. The method of claim 1 wherein the step of raising the first supply voltage comprises raising the first supply voltage from 0.6 volts to 1.4 volts.
4. The method of claim 1 further comprising raising a voltage on the complementary bit line pair from a standby voltage before the step of raising the word line voltage.
5. The method of claim 4 wherein the step of raising the complementary bit line pair voltage comprises raising the voltage from 0.6 volts to 1.4 volts.
6. For an integrated circuit having an array of SRAM cells interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each SRAM cell having a pair of cross-coupled thyristors, each thyristor having first and second semiconductor regions intermediate an anode and a cathode, a first intermediate region of one thyristor connected to the second intermediate region of the other thyristor and a second intermediate region of the one thyristor connected to the first intermediate region of the other thyristor, each thyristor having an anode connected to a first supply voltage and a cathode connected to a second supply voltage, and a pair of bipolar select transistors, each bipolar select transistor having a collector region connected to one of a complementary bit line pair, and an emitter region connected to the first intermediate region of one of the thyristors, and having a base region connected to a word line, a method of reading an SRAM cell in the array, comprising:
selecting at least one SRAM cell;
raising the voltage on the word line connected to the bipolar select transistors of the selected SRAM cell from a word line standby voltage;
raising a voltage on the complementary bit line pair from a standby voltage before the step of raising the word line voltage; and
raising the first supply voltage from a first supply standby voltage, the first supply voltage below the raised word line voltage;
whereby a state of the at least one selected SRAM cell is read through a complementary bit line pair connected to the bipolar select transistors of the at least one selected SRAM cell.
7. The method of claim 6 wherein the step of raising the word line voltage comprises raising the word line voltage from 0.0 volts to 1.6 volts.
8. The method of claim 6 wherein the step of raising the first supply voltage comprises raising the first supply voltage from 0.6 volts to 1.4 volts.
9. The method of claim 6 wherein the step of raising the complementary bit line pair voltage comprises raising the voltage from 0.6 volts to 1.4 volts.
10. For an integrated circuit having an array of SRAM cells interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each SRAM cell having a pair of cross-coupled thyristors, each thyristor having first and second semiconductor regions intermediate an anode and a cathode, a first intermediate region of one thyristor connected to the second intermediate region of the other thyristor and a second intermediate region of the one thyristor connected to the first intermediate region of the other thyristor, each thyristor having an anode connected to a first supply voltage and a cathode connected to a second supply voltage, and a pair of bipolar select transistors, each bipolar select transistor having a collector region connected to one of a complementary bit line pair, and an emitter region connected to the first intermediate region of one of the thyristors, and having a base region connected to a word line, a method of reading an SRAM cell in the array, comprising:
selecting at least one SRAM cell;
raising the voltage on the word line connected to the bipolar select transistors of the selected SRAM cell from a word line standby voltage; and
raising the first supply voltage from a first supply standby voltage, the first supply voltage below the raised word line voltage, the step of raising the word line voltage delayed with respect to the step of raising the first supply voltage;
whereby a state of the at least one selected SRAM cell is read through a complementary bit line pair connected to the bipolar select transistors of the at least one selected SRAM cell.
11. The method of claim 10 wherein the step of raising the word line voltage comprises raising the word line voltage from 0.0 volts to 1.6 volts.
12. The method of claim 10 wherein the step of raising the first supply voltage comprises raising the first supply voltage from 0.6 volts to 1.4 volts.
13. The method of claim 10 further comprising raising a voltage on the complementary bit line pair from a standby voltage before the step of raising the word line voltage.
14. The method of claim 13 wherein the step of raising the complementary bit line pair voltage comprises raising the voltage from 0.6 volts to 1.4 volts.
15. The method of claim 10 wherein the step of raising the word line voltage is delayed with respect to the step of raising the first supply voltage from 10-60 picoseconds.
16. The method of claim 15 wherein the step of raising the word line voltage comprises raising the word line voltage from 0 volts to 1.6 volts.
17. The method of claim 15 wherein the step of raising the first supply voltage comprises raising the first supply voltage from 0.6 volts to 1.4 volts.
18. The method of claim 10 further comprising raising a voltage on the complementary bit line pair from a standby voltage before the step of raising the word line voltage.
19. The method of claim 18 wherein the step of raising the complementary bit line pair voltage comprises raising the voltage from 0.6 volts to 1.4 volts.