Memory device based on heterostructures of ferroelectric and two-dimensional materials
A ferroelectric random-access memory structure and processes for fabricating a ferroelectric random-access memory structure are described that includes using a molybdenum sulfide layer. In an implementation, a ferroelectric random-access memory structure in accordance with an exemplary embodiment includes at least one FeFET, which further includes a substrate; a back gate electrode formed on the substrate, the back gate electrode including a conductive layer; a gate dielectric substrate formed on the back gate electrode; a source electrode formed on the gate dielectric substrate; a drain electrode formed on the gate dielectric substrate; and a layered transition metal dichalcogenide disposed on the gate dielectric substrate and contacting the source electrode and the drain electrode.
1. A ferroelectric random-access memory structure, comprising:
at least one FeFET including
a substrate;
a back gate electrode formed on the substrate, the back gate electrode including a conductive layer;
a gate dielectric substrate formed on the back gate electrode;
a source electrode formed on the gate dielectric substrate;
a drain electrode formed on the gate dielectric substrate; and
a bridge disposed on the gate dielectric substrate and contacting the source electrode and the drain electrode, wherein the bridge consists essentially of a layered transition metal dichalcogenide.
2. The ferroelectric random-access memory structure of claim 1 , wherein the substrate includes a Si/SiO 2 substrate.
3. The ferroelectric random-access memory structure of claim 1 , wherein the conductive layer includes a TiO 2 /Ir layer.
4. The ferroelectric random-access memory structure of claim 1 , wherein the gate dielectric substrate includes a lead zirconium titanate (PZT) substrate.
5. The ferroelectric random-access memory structure of claim 1 , wherein the gate dielectric substrate includes a barium titanate substrate.
6. The ferroelectric random-access memory structure of claim 1 , wherein the source electrode includes a titanium gold (Ti/Au) source electrode.
7. The ferroelectric random-access memory structure of claim 1 , wherein the drain electrode includes a titanium gold (Ti/Au) drain electrode.
8. The ferroelectric random-access memory structure of claim 1 , wherein the layered transition metal dichalcogenide includes at least one of molybdenum disulfide (MoS2) or tungsten disulfide (WS 2 ) and wherein the layered transition metal dichalcogenide is a monolayer or multilayer.
9. A ferroelectric random-access memory structure, comprising:
at least one ferroelectric tunnel junction including
a substrate;
a bottom electrode formed on the substrate;
a ferroelectric barrier having a thickness less than 5 nanometers formed on the bottom electrode; and
a layered transition metal dichalcogenide disposed on the ferroelectric barrier.
10. The ferroelectric random-access memory structure of claim 9 , wherein the substrate includes a Si/SiO 2 substrate.
11. The ferroelectric random-access memory structure of claim 9 , wherein the ferroelectric barrier includes a lead zirconium titanate (PZT) substrate.
12. The ferroelectric random-access memory structure of claim 9 , wherein the ferroelectric barrier includes a barium titanate substrate.
13. The ferroelectric random-access memory structure of claim 9 , further comprising:
an adsorbate water layer disposed at a layered transition metal dichalcogenide and ferroelectric barrier interface.