Post CMOS compatible ferroelectric field effect transistor with AlScN dielectric and 2D material channel
Provided are ferroelectric field effect transistor (FeFET) based memory devices. These devices include aluminum scandium nitride (AlScN) as a ferroelectric dielectric and 2D chalcogenide semiconductors as a semiconductor channel in the transistor. The disclosed materials, devices and fabrication processes involved are compatible with back end of the line (BEOL) processing of a silicon based microchip and also compatible with silicon microprocessor fabrication.
1 . A component, comprising:
a portion of AlScN that is 0001 or 0002-oriented crystal in form;
a semiconducting channel portion,
the channel portion being in electronic communication with the portion of AlScN, and
the channel portion comprising a material characterized as a 2D semiconducting metal chalcogenide,
a 111-oriented metal back-gate electrode contacting the portion of AlScN;
a metallic source electrode in electronic communication with the channel portion; and
a metallic drain electrode in electronic communication with the channel portion,
the metallic source electrode being superposed over the semiconducting channel portion, and the semiconducting channel portion being superposed over the portion of AlScN such that the metallic source electrode is superposed over the portion of AlScN.
2 . The component of claim 1 , wherein the channel portion is disposed on the portion of AlScN.
3 . The component of claim 1 , wherein the channel portion is characterized as comprising a plurality of monolayers of the 2D semiconducting metal chalcogenide.
4 . The component of claim 1 , wherein the 2D semiconducting metal chalcogenide comprises MoS 2 , WS 2 , WSe 2 , MoTe 2 , InSe, SnSe, GaSe, CrGeTe, black phosphorus, tellurene, arsenene, selenene or any combination thereof.
5 . The component of claim 1 , wherein the portion of AlScN defines a thickness in the range of from about 2 to about 50 nm.
6 . The component of claim 1 , wherein the channel portion defines a thickness in the range of from about 0.5 to about 1.2 nm.
7 . The component of claim 1 , wherein the component exhibits a memory window/thickness in the range of from about 0.05 to about 0.4 V/nm.
8 . The component of claim 1 , wherein the component exhibits an on/off ratio of from about 10 to about 107.
9 . The component of claim 1 , wherein (a) the back-gate electrode contacts the AlScN portion, (b) the source electrode contacts the channel, (c) the drain electrode contacts the channel, or any combination of (a), (b), and (c).
10 . The component of claim 1 , wherein the component exhibits a counterclockwise hysteresis loop under a relatively larger gate voltage sweep of and a negligible hysteresis loop under a relatively smaller gate voltage sweep as compared to the relatively larger gate voltage sweep.
11 . The component of claim 1 , wherein the back-gate electrode has a thickness of from about 5 to about 200 nm, wherein the AlScN portion has a thickness of from about 5 nm to about 500 nm, wherein the semiconducting channel portion has a thickness of from about 0.5 to about 5 nm, wherein the source electrode has a thickness of from about 10 nm to about 100 nm, and wherein the drain electrode has a thickness of from about 10 nm to about 100 nm.
12 . The component of claim 1 , wherein either one or both of the source electrode and the drain electrode independently comprises Ti, Cr, Au, or Pd.
13 . The component of claim 1 , wherein the semiconducting character of the material corresponds to n-type.
14 . The component of claim 1 , wherein the semiconducting character of the material corresponds to ambipolar.
15 . The component of claim 14 , wherein the component is characterized as having two stable voltage-induced states at positive gate voltages, and wherein the component is characterized as having two stable voltage-induced states at negative gate voltages.
16 . A method, comprising applying a voltage to a component according to claim 1 .
17 . The method of claim 16 , wherein the voltage switches the component from a persistent first state to a persistent second state.
18 . A method, comprising:
fabricating a component according to claim 1 ,
the fabricating being performed at less than about 400 deg. C.
19 . The component of claim 1 , further comprising an oxide layer disposed between the portion of AlScN and the semiconducting channel portion.
20 . The component of claim 1 , wherein the 111-oriented metal back-gate electrode comprises Pt.
21 . The component of claim 1 , wherein the metallic drain electrode is superposed over the semiconducting channel portion, and the semiconducting channel portion is superposed over the portion of AlScN such that the metallic drain electrode is superposed over the portion of AlScN.
22 . The component of claim 1 , wherein the component is free from a depolarization capacitor for depolarizing the semiconductor channel.
23 . The component of claim 1 , wherein the portion of AlScN defines a thickness in the range of from about 2 to about 50 nm, wherein the channel portion defines a thickness in the range of from about 0.5 to about 1.2 nm, and wherein the 2D semiconducting metal chalcogenide comprises MoS 2 , WS 2 , WSe 2 , MoTe 2 , InSe, SnSe, GaSe, CrGeTe, black phosphorus, tellurene, arsenene, selenene or any combination thereof.