IP Library Granted Patent US 9,793,265
Granted Patent B2
US 9,793,265 · App. 15/265,940 · Granted Oct 17, 2017

Semiconductor device including Schottky barrier diode and power MOSFETs and a manufacturing method of the same

Inventors: Masaki Shiraishi (Hitachi, JP); Tomoaki Uno (Takasaki, JP); Nobuyoshi Matsuura (Takasaki, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L27/0629H01L21/28035H01L21/823475H01L23/3107H01L23/49524H01L23/49562H01L23/49575H01L24/06H01L24/40H01L24/49H01L24/73H01L29/4236H01L29/45H01L29/4916H01L29/66143H01L29/66734H01L29/7806H01L29/7813H02M3/155H02M7/003H01L24/45H01L24/48H01L29/1095H01L29/41741H01L29/4232H01L29/4238H01L29/456H01L29/872H01L2224/0401H01L2224/04042H01L2224/05554H01L2224/05624H01L2224/40095H01L2224/40245H01L2224/40247H01L2224/45015H01L2224/45144H01L2224/48011H01L2224/48091H01L2224/48095H01L2224/48137H01L2224/48247H01L2224/48253H01L2224/48624H01L2224/4903H01L2224/49051H01L2224/49111H01L2224/49171H01L2224/49175H01L2224/73221H01L2924/01002H01L2924/01004H01L2924/014H01L2924/0105H01L2924/01005H01L2924/01006H01L2924/01013H01L2924/01014H01L2924/01015H01L2924/01021H01L2924/01022H01L2924/01023H01L2924/01027H01L2924/01028H01L2924/01029H01L2924/01033H01L2924/01046H01L2924/01047H01L2924/01057H01L2924/01072H01L2924/01074H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/12032H01L2924/1305H01L2924/1306H01L2924/13091H01L2924/14H01L2924/1532H01L2924/181H01L2924/19041H01L2924/19043H01L2924/20753H01L2924/20755H01L2924/3011H01L2924/30105H01L2924/30107
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Quick Facts
Patent No.
US 9,793,265
App. No.
15/265,940
Filed
Sep 15, 2016
Granted
Oct 17, 2017
Kind
B2
Art Unit
2817
USPC
438/237
Abstract

In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Claims (26)

1. A method of forming a semiconductor device, comprising:

(a) preparing a semiconductor wafer having a semiconductor device forming region,

wherein the semiconductor device forming region includes a first long side, a second long side located on the opposite side of the first long side, a first short side and a second short side located on the opposite side of the first short side,

wherein a schottky barrier diode is formed in a first region of the semiconductor device forming region and includes an anode and a cathode,

wherein a plurality of power MOSFETs are formed in a plurality of second regions of the semiconductor device forming region and respectively include a gate electrode, a source region and a drain region,

(b) forming an insulating film over the semiconductor device forming region;

(c) forming a metal layer over the insulating film; and

(d) forming a first metal layer and a second metal layer by patterning the metal layer;

wherein the first region is arranged between the first long side and the second long side,

wherein the plurality of second regions are arranged along the first long side, and are arranged between the first long side and the first region,

wherein the first metal layer is connected to the gate electrodes, and includes a first finger portion and a second finger portion,

wherein the first finger portion extends along the first long side, and the second finger portion extends along the first short side and the second finger portion is arranged between the plurality of second regions,

wherein the second metal layer is connected to the source regions in the plurality of second regions and the anode in the first region, and

wherein a first length of the first region along the first long side is larger than a second length of the first region along the first short side.

2. A method of forming a semiconductor device according to the claim 1 , further comprising:

further second regions having further power MOSFETs each including a further gate electrode, a further source region and a further drain region,

wherein, in the direction along the first short side, the first region is arranged between the second region arranged near the first long side and the further second region arranged near the second long side.

3. A method of forming a semiconductor device according to the claim 1 ,

wherein the first metal layer further includes a third finger portion and a fourth finger portion,

wherein the third finger portion extends along the second long side, and the fourth finger portion extends along the first short side and the fourth finger portion is arranged between the plurality of further second regions, and

wherein the second metal layer is connected to the source regions in further second regions.

4. A method of forming a semiconductor device according to the claim 1 ,

wherein each of the gate electrodes is formed in grooves formed in the semiconductor wafer.

5. A method of forming a semiconductor device according to the claim 1 ,

wherein each of the gate electrodes includes a poly silicon film, and

wherein the metal layer includes an aluminum film.

Assignments (1)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
Priority Claims (1)
JP 2004-223664 · Jul 30, 2004 · national
Continuity (8)
Continuation 14857596 · Sep 17, 2015
Continuation 14340198 · Jul 24, 2014
Continuation 14072047 · Nov 5, 2013
Continuation 13588538 · Aug 17, 2012
Continuation 13396073 · Feb 14, 2012
Continuation 12686595 · Jan 13, 2010
Continuation 11192069 · Jul 29, 2005
Related Publication 20170005089A1 · Jan 5, 2017